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DAC38RF82

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Dual-Channel, 14-Bit, 9-GSPS, 1x-24x Interpolating, 6 & 9 GHz PLL Digital-to-Analog Converter (DAC)

Data sheet
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Dual-Channel, 14-Bit, 9-GSPS, 1x-24x Interpolating, 6 & 9 GHz PLL Digital-to-Analog Converter (DAC)

DAC38RF82

ACTIVE
Data sheet Order now

Product details

Parameters

Resolution (Bits) 14 Sample/update rate (MSPS) 9000 Number of DAC channels (#) 2 Interpolation 10x, 12x, 16x, 18x, 1x, 20x, 24x, 2x, 4x, 6x, 8x Power consumption (Typ) (mW) 3800 Operating temperature range (C) -40 to 85 open-in-new Find other Transmitters

Package | Pins | Size

FCBGA (AAV) 144 100 mm² 10 x 10 open-in-new Find other Transmitters

Features

  • 14-Bit resolution, 9-GSPS DAC with multimode operation
    • 16-Bit, Dual-channel data mode
      • Max input rate: 2.5-GSPS
      • Wideband digital up-converter
        • Interpolation: 1,2,4,6,8,10,12,16,18,20,24x
    • 12-Bit, Dual-channel data mode
      • Max input rate: 3.33-GSPS
      • Wideband digital Up-converter
        • Interpolation: 1,2,24x
    • 8-Bit, Single-channel data mode
      • Max input rate: 9-GSPS
  • JESD204B interface
    • Subclass 1 for multichip synchronization
    • DAC38RF89: Maximum lane rate: 12.5 Gbps
    • DAC38RF82: Maximum lane rate: 12.8 Gbps
  • Differential output
    • Supports DC coupling
    • RF Full-scale output power (with 2:1 balun):
      3 dBm at 2.14 GHz
  • Internal PLL and VCO with bypass
    • DAC38RF82: fC(VCO) = 5.9 or 8.9 GHz
    • DAC38RF89: fC(VCO) = 5 or 7.5 GHz
  • Power supplies: -1.8 V, 1.0 V, 1.8 V
  • Package: 10 x 10 mm BGA, 0.8 mm pitch,
    144-balls

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Description

The DAC38RF82 and DAC38RF89 are high performance, wide bandwidth RF-sampling digital-to-analog (DACs) that are capable of dual channel input data rate up to 3.33 GSPS or single-channel operation with 8-bits up to 9-GSPS. The devices have a low power JESD204B Interface with up to 8 lanes, with a maximum bit rate of 12.5 Gbps (DAC38RF89) and 12.8 Gbps (DAC38RF82).

In dual channel operation, the input interface is capable of data rates up to 3.33 GSPS at 12-bits and 2.5 GSPS at 16-bits resolution without interpolation. When used as a complex baseband transmitter with interpolation modes from 2x to 24x, the DAC38RF82 or DAC38RF89 is capable of synthesizing wideband signals up to 2 GHz bandwidth with 16-bit input resolution and 2.66 GHz bandwidth with 12-bit input resolution.

The 8-bit mode allows an input at the full 9 GSPS maximum DAC sample rate and can synthesize wideband signals from 0 to 4.5 GHz.

An optional low jitter PLL/VCO simplifies the DAC clock generation by allowing use of a lower frequency reference clock. DAC38RF82 and DAC38RF89 support different VCO frequency ranges, summarized in Device Comparison Table.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 14
Type Title Date
* Datasheet DAC38RF8x Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation datasheet (Rev. D) Apr. 14, 2020
Application note Impact of Power-Supply Noise on Phase Noise Performance of RF DACs Jun. 13, 2018
User guide TSW40RF8x Evaluation Module User's Guide (Rev. A) Sep. 27, 2017
Application note Eye Scan Testing with the DAC38RFxx Aug. 10, 2017
Application note Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer Information Aug. 02, 2017
Application note DAC38RF8x Test Modes Jul. 25, 2017
Technical articles Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
User guide DAC38RF8xEVM User's Guide (Rev. A) Mar. 24, 2017
Technical articles Digital signal processing in RF sampling DACs - part 1 Feb. 13, 2017
Application note Digital RF Power Control for Power Amplifer Protection in Wireless Base Feb. 06, 2017
Application note RF Sampling DAC with 800 MHz of IBW LTE Oct. 28, 2016
User guide Efficient Power Supply Scheme for RF-Sampling DAC Reference Design Aug. 22, 2016
Technical articles RF sampling: digital mixers make mixing fun Sep. 17, 2015
Technical articles How our high-speed DAC summation block can help you Apr. 02, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
Description
The DAC38RF82EVM is the circuit board for evaluating DAC38RF82/83/85/93 digital to analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9GSPS sampling rate and it is designed to work with the TSW14J56 EVM. The available FMC connector also makes it possible to (...)
Features
  • Allows evaluation of DAC38RF82/83/85/93 up to 9GSPS sampling rate
  • Supports up to 12.5Gbps serdes signaling rate across FMC
  • Integrated low phase noise On–chip PLL with 2 VCOs to simplify system clock generation. Also supports external clock mode.
  • AC coupled, differential output with on-board 2:1 (...)
View details
EVALUATION BOARD Download
2499
Description

The TSW40RF82 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF82 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The DAC38RF82 (...)

Features
  • RF-sampling transceiver utilizing the JESD204B interface
  • DAC38RF82 dual RF DAC with differential output
  • ADC32RF45 dual RF ADC with bypass option
  • LDO-less power-management solution
  • Onboard clocking solution; four different ADC clocking options, including TX PLL clock output
  • Interfaces with TSW14J56 or FPGA (...)
View details

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP — The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
View details
FIRMWARE Download
SLAC771A.ZIP (10836 KB)
FIRMWARE Download
SLAC779A.ZIP (48623 KB)
GUI FOR EVALUATION MODULE (EVM) Download
SLAC722D.ZIP (216778 KB)

Design tools & simulation

SIMULATION MODEL Download
SLAM304.ZIP (70 KB) - IBIS Model
SIMULATION MODEL Download
SLAM343.ZIP (24819 KB) - IBIS-AMI Model
SCHEMATIC Download
SLAC734.ZIP (10565 KB)

Reference designs

REFERENCE DESIGNS Download
Power Supply Reference Design for Optimizing Spur and Phase Noise in RF-sampling DACs
TIDA-01215 — This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x while (...)
document-generic Schematic
REFERENCE DESIGNS Download
High-Bandwidth Zero-IF Reference Design for Microwave Backhaul
TIDA-01435 — The TSW40RF82EVM reference design provides a platform to interface the DAC38RF82 with a high-performance modulator - the TRF370417EVM. The TRF370417EVM can modulate wideband signals at up to 6 GHz as would be typical for a microwave backhaul application. The TRF370417 device may be substituted for a (...)
document-generic Schematic
Design files
View details

CAD/CAE symbols

Package Pins Download
FCBGA (AAV) 144 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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