Product details


Resolution (Bits) 14 Sample/update rate (MSPS) 8400 Number of DAC channels (#) 2 Interpolation 10x, 12x, 16x, 18x, 1x, 20x, 24x, 2x, 4x, 6x, 8x Power consumption (Typ) (mW) 3800 Operating temperature range (C) -40 to 85 open-in-new Find other Transmitters

Package | Pins | Size

FCBGA (AAV) 144 100 mm² 10 x 10 open-in-new Find other Transmitters


  • 14-Bit resolution, 9-GSPS DAC with multimode operation
    • 16-Bit, Dual-channel data mode
      • Max input rate: 2.5-GSPS
      • Wideband digital up-converter
        • Interpolation: 1,2,4,6,8,10,12,16,18,20,24x
    • 12-Bit, Dual-channel data mode
      • Max input rate: 3.33-GSPS
      • Wideband digital Up-converter
        • Interpolation: 1,2,24x
    • 8-Bit, Single-channel data mode
      • Max input rate: 9-GSPS
  • JESD204B interface
    • Subclass 1 for multichip synchronization
    • DAC38RF89: Maximum lane rate: 12.5 Gbps
    • DAC38RF82: Maximum lane rate: 12.8 Gbps
  • Differential output
    • Supports DC coupling
    • RF Full-scale output power (with 2:1 balun):
      3 dBm at 2.14 GHz
  • Internal PLL and VCO with bypass
    • DAC38RF82: fC(VCO) = 5.9 or 8.9 GHz
    • DAC38RF89: fC(VCO) = 5 or 7.5 GHz
  • Power supplies: -1.8 V, 1.0 V, 1.8 V
  • Package: 10 x 10 mm BGA, 0.8 mm pitch,

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The DAC38RF82 and DAC38RF89 are high performance, wide bandwidth RF-sampling digital-to-analog (DACs) that are capable of dual channel input data rate up to 3.33 GSPS or single-channel operation with 8-bits up to 9-GSPS. The devices have a low power JESD204B Interface with up to 8 lanes, with a maximum bit rate of 12.5 Gbps (DAC38RF89) and 12.8 Gbps (DAC38RF82).

In dual channel operation, the input interface is capable of data rates up to 3.33 GSPS at 12-bits and 2.5 GSPS at 16-bits resolution without interpolation. When used as a complex baseband transmitter with interpolation modes from 2x to 24x, the DAC38RF82 or DAC38RF89 is capable of synthesizing wideband signals up to 2 GHz bandwidth with 16-bit input resolution and 2.66 GHz bandwidth with 12-bit input resolution.

The 8-bit mode allows an input at the full 9 GSPS maximum DAC sample rate and can synthesize wideband signals from 0 to 4.5 GHz.

An optional low jitter PLL/VCO simplifies the DAC clock generation by allowing use of a lower frequency reference clock. DAC38RF82 and DAC38RF89 support different VCO frequency ranges, summarized in Device Comparison Table.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 11
Type Title Date
* Datasheet DAC38RF8x Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation datasheet (Rev. D) Apr. 14, 2020
Application notes Impact of Power-Supply Noise on Phase Noise Performance of RF DACs Jun. 13, 2018
Application notes Eye Scan Testing with the DAC38RFxx Aug. 10, 2017
Application notes Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer Information Aug. 02, 2017
Application notes DAC38RF8x Test Modes Jul. 25, 2017
Technical articles Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
User guides DAC38RF8xEVM User's Guide (Rev. A) Mar. 24, 2017
Technical articles Digital signal processing in RF sampling DACs - part 1 Feb. 13, 2017
User guides Efficient Power Supply Scheme for RF-Sampling DAC Reference Design Aug. 22, 2016
Technical articles RF sampling: digital mixers make mixing fun Sep. 17, 2015
Technical articles How our high-speed DAC summation block can help you Apr. 02, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The DAC38RF89 evaluation module (EVM) is the circuit board for evaluating DAC38RF89 digital-to-analog converters (DACs). The DAC38RFEVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC (...)

  • Allows evaluation of DAC38RF89 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (DAC38RF89) for (...)
SLAC722D.ZIP (216778 KB)

Software development

SLAC779A.ZIP (48623 KB)

Design tools & simulation

SLAM304.ZIP (70 KB) - IBIS Model
SLAC734.ZIP (10565 KB)

Reference designs

Power Supply Reference Design for Optimizing Spur and Phase Noise in RF-sampling DACs
TIDA-01215 — This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x while (...)
document-generic Schematic document-generic User guide

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