This feature is useful to make sure that communication between the host processor and the DACx760 has not been lost. Enable the watchdog timer by setting the WDEN bit of the Configuration Register to 1. The watchdog timeout period can be set using the WDPD bits of the configuration register; see Table 8-3. The timer period is based off an internal oscillator with a typical value of 8 MHz.
|WDPD BITS||WATCHDOG TIMEOUT PERIOD (Typical, ms)|
If enabled, the chip must have an SPI frame with 0x95 as the write address byte written to the device within the programmed timeout period. Otherwise, the ALARM pin asserts low and the WD-FLT bit of the status register is set to 1. The ALARM pin can be asserted low for any of the different conditions, as explained in Section 8.3.8. To reset the WD-FLT bit to 0, use a software reset, disable the watchdog timer, or power down the device.