When the VOUT and IOUT pins are tied together, bit 8 of the Configuration Register (DUAL OUTEN) must be set to 0. Bits 2 down to 0 of the Control Register (RANGE) control VOUT and IOUT. Special consideration must be paid to the +VSENSE pin in this case. When VOUT is disabled, the +VSENSE pin is connected to the internal amplifier input through an internal 60-kΩ resistor as shown in Figure 8-2. This internal node has diode clamps to REFIN and GND. Setting bit 6 of the Configuration Register (APD) forces this internal node to be tied to GND through a 10-kΩ resistor, in effect, the +VSENSE pin is tied to GND through a 70-kΩ power-down resistor. Figure 9-1 shows the leakage current into the +VSENSE pin for both settings of the APD bit.
Whether the APD bit is set or not set, the current output in this case incurs a gain error because the internal resistor acts as a parallel load in addition to the external load. If this gain error is undesirable, it can be corrected through the gain calibration register shown in Table 8-20. Another option is to use the application circuit in Figure 9-2.
The buffer amplifier prevents leakage through the internal 60-kΩ resistor in current output mode and does not allow it to be seen as a parallel load. The VOUT pin is in high impedance mode in this case and allows minimal leakage current. Note that the offset of the external amplifier adds to the overall VOUT offset error and any potential phase shift from the external amplifier can cause VOUT stability issues.