The DACx760 configuration register is written to at address 0x57. Table 8-18 summarizes the description for the configuration register bits.
|DB15:DB11||0h||Reserved. User must not write any value other than zero to these bits.|
|DB10:DB9||IOUT RANGE||00||IOUT range. These bits are only used if both voltage and current outputs are simultaneously enabled through bit 8 (DUAL OUTEN). The voltage output range is still controlled by bits 2:0 of the Control Register (RANGE bits). The current range is controlled by these bits and has similar behavior to RANGE[1:0] when RANGE = 1. However, unlike the RANGE bits, a change to this field does not make the DAC data register go to its default value.|
|DB8||DUAL OUTEN||0||DAC dual output enable. This bit controls if the voltage and current outputs are enabled simultaneously. Both are enabled when this bit is high. However, both outputs are controlled by the same DAC data register.|
|DB7||APD||0||Alternate power down. On power-up, +VSENSE is connected to the internal VOUT amplifier inverting pin. Diodes exist at this node to REFIN and GND. Setting this bit connects this node to ground through a resistor. When set, the equivalent resistance seen from +VSENSE to GND is 70 kΩ. This is useful in applications where the VOUT and IOUT pins are tied together.|
|DB6||0||Reserved. Do not write any value other than zero to these bits.|
|DB5||CALEN||0||User calibration enable. When user calibration is enabled, the DAC data are adjusted according to the contents of the gain and zero calibration registers. See Section 8.3.11.|
interface through HART-IN pin (only valid for IOUT set to 4-mA to
20-mA range through RANGE bits).
Bit = 1: HART signal is connected through internal resistor and modulates output current.
Bit = 0: HART interface is disabled.
|DB3||CRCEN||0||Enable frame error checking.|
|DB2||WDEN||0||Watchdog timer enable.|
|DB1:DB0||WDPD[1:0]||00||Watchdog timeout period.|