The DACx760 control register is written to at address 0x55. Table 8-17 shows the description for the control register bits.
|DB15||CLRSEL||0||VOUT clear value select bit.|
When bit = 0, VOUT is 0 V in Section 8.3.6 mode or after reset.
When bit = 1, VOUT is midscale in unipolar output and negative-full-scale in bipolar output in Section 8.3.6 mode or after reset.
|DB14||OVR||0||Setting the bit increases the voltage output range by 10%.|
|DB13||REXT||0||External current setting resistor enable.|
|DB12||OUTEN||0||Output enable. |
Bit = 1: Output is determined by RANGE bits.
Bit = 0: Output is disabled. IOUT and VOUT are Hi-Z.
|DB11:DB8||SRCLK[3:0]||0000||Slew rate clock control. Ignored when bit SREN = 0|
|DB7:DB5||SRSTEP[2:0]||000||Slew rate step size control. Ignored when bit SREN = 0|
|DB4||SREN||0||Slew Rate Enable. |
Bit = 1: Slew rate control is enabled, and the ramp speed of the output change is determined by SRCLK and SRSTEP.
Bit = 0: Slew rate control is disabled. Bits SRCLK and SRSTEP are ignored. The output changes to the new level immediately.
|DB3||Reserved||0||Reserved. Must be set to 0.|
|DB2:DB0||RANGE[2:0]||000||Output range bits.|