SBAS528C June   2013  – January 2018 DAC7760 , DAC8760

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Requirements: Daisy-Chain Mode
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Current Output Stage
      4. 8.3.4  Internal Reference
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  DAC Clear
      7. 8.3.7  Power-Supply Sequence
      8. 8.3.8  Power-On Reset
      9. 8.3.9  Alarm Detection
      10. 8.3.10 Watchdog Timer
        1. 8.3.10.1 The DACx760 Shares the SPI Bus With Other Devices (Non-DACx760)
      11. 8.3.11 Frame Error Checking
        1. 8.3.11.1 The DACx760 Shares the SPI Bus With Other Devices (Non-DACx760)
      12. 8.3.12 User Calibration
      13. 8.3.13 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Voltage and Current Output Ranges
      2. 8.4.2 Boost Configuration for IOUT
      3. 8.4.3 Filtering the Current Output (only on the VQFN package)
      4. 8.4.4 HART Interface
        1. 8.4.4.1 For 4-mA to 20-mA Mode
        2. 8.4.4.2 For All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Daisy-Chain Operation
    6. 8.6 Register Maps
      1. 8.6.1 DACx760 Commands and Register Map
        1. 8.6.1.1 DACx760 Register Descriptions
          1. 8.6.1.1.1 Control Register
          2. 8.6.1.1.2 Configuration Register
          3. 8.6.1.1.3 DAC Registers
          4. 8.6.1.1.4 Reset Register
          5. 8.6.1.1.5 Status Register
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Controlling the VOUT and IOUT Pins
        1. 9.1.1.1 VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled
        2. 9.1.1.2 VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled
        3. 9.1.1.3 VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled
      2. 9.1.2 Implementing HART in All Current Output Modes
        1. 9.1.2.1 Using CAP2 Pin on VQFN Package
        2. 9.1.2.2 Using the ISET-R Pin
      3. 9.1.3 Short-Circuit Current Limiting
    2. 9.2 Typical Application
      1. 9.2.1 Voltage and Current Output Driver for Factory Automation and Control, EMC and EMI Protected
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

Layout Guidelines

To maximize the performance of the DACx760 in any application, good layout practices and proper circuit design must be followed. A few recommendations specific to the DACx760 are:

  1. As is seen in Figure 93, CAP2 is directly connected to the input of the final IOUT amplifier. Any noise or unwanted ac signal routed near the CAP1 and/or CAP2 pins could capacitively couple onto internal nodes and affect IOUT. Therefore, with the QFN package, it is important to avoid routing any digital or HART signal trace over the CAP1 and CAP2 traces.
  2. The thermal PAD must be connected to the lowest potential in the system.
  3. The +VSENSE connection must be a low-impedance trace connected close to the point of load.
  4. AVDD and AVSS must have decoupling capacitors local to the respective pins.
  5. The reference capacitor must be placed close to the reference input pin.
  6. Avoid routing switching signals near the reference input.
  7. For designs that include protection circuits:
    1. Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices.
    2. Use large, wide traces to provide a low-impedance path to divert high-energy transients away from I/O terminals.

Layout Example

DAC7760 DAC8760 layout_example_sbas528.gif Figure 100. DACx760 Layout Example

Thermal Considerations

The DACx760 is designed for a maximum junction temperature of +150°C. In cases where the maximum AVDD is driving maximum current into ground, this could be exceeded. Use the following equation, from the Absolute Maximum Ratings, to determine the maximum junction temperature that can be reached:

Equation 8. Power Dissipation = (TJmax – TA)/θJA

where

  • TJmax = 150°C
  • TA is the ambient temperature
  • θJA is the package dependent junction-to-ambient thermal resistance, which is found in Thermal Information

The power dissipation can be calculated by multiplying all the supply voltages with the currents supplied, which is found in the Power Requirements subsection of Electrical Characteristics.

Consider an example: IOUT is enabled, supplying 24 mA into GND with a 25°C ambient temperature, AVDD of 24 V, AVSS is tied to GND and DVDD is generated internally. From the specifications table, the maximum value of AIDD = 3 mA when IOUT is enabled and DAC code = 0x0000. Also, the maximum value of DIDD = 1 mA. Accordingly, the worst case power dissipation is 24 V × (24 mA + 3 mA + 1 mA) = 672 mW. Using the RθJA value for the TSSOP package, we get TJmax = 25°C + (32.3 × 0.672)°C = 46.7°C. At 85°C ambient temperature, the corresponding value of TJmax is 106.7°C. Using this type of analysis, the system designer can both specify and design for the equipment operating conditions. Note that the thermal pad in both packages is recommended to be connected to a copper plane for enhanced thermal performance.