DLPS258 Data sheet

DLPS258 August 2025 DLP472NP

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

FQY|174
- MCLG050

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

		MIN	MAX	UNIT
SUPPLY VOLTAGE
V_DD	Supply voltage for LVCMOS core logic and LPSDR low speed interface ⁽¹⁾	-0.5	2.3	V
V_DDI	Supply voltage for SubLVDS receivers⁽¹⁾	-0.5	2.3	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode⁽¹⁾⁽²⁾	-0.5	11	V
V_BIAS	Supply voltage for micromirror electrode⁽¹⁾	-0.5	19	V
V_RESET	Supply voltage for micromirror electrode⁽¹⁾	-15	0.5	V
\|V_DDI - V_DD\|	Supply voltage delta, absolute value⁽³⁾		0.3	V
\|V_BIAS - V_OFFSET\|	Supply voltage delta, absolute value⁽⁴⁾		11	V
\|V_BIAS - V_RESET\|	Supply voltage delta, absolute value⁽⁵⁾		34	V
INPUT VOLTAGE
	Input voltage for other inputs—LSIF and LVCMOS⁽¹⁾	-0.5	V_DD + 0.5	V
	Input voltage for other inputs—SubLVDS⁽¹⁾⁽⁶⁾	-0.5	V_DDI + 0.5	V
SUBLVDS INTERFACE
\|V_ID\|	SubLVDS input differential voltage (absolute value)⁽¹⁾⁽⁶⁾		810	mV
I_ID	SubLVDS input differential current		10	mA
CLOCK FREQUENCY
ƒ_clock	Clock frequency for low-speed interface LS_CLK	100	130	MHz
TEMPERATURE DIODE
I_{TEMP_DIODE}	Max current source into the temperature diode		120	µA
ENVIRONMENTAL
T_WINDOW and T_ARRAY	Temperature, operating⁽⁷⁾	0	90	°C
T_WINDOW and T_ARRAY	Temperature, non-operating⁽⁷⁾	-40	90	°C
\|T_DELTA\|	Absolute temperature delta between any point on the window edge and the ceramic test point TP1⁽⁸⁾		30	°C
T_DP	Dew point temperature, operating and non-operating (noncondensing)		81	°C

(1) All voltage values are for the ground terminals (V_SS). The following required power supplies must be connected for proper DMD operation: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are also required.

(2) V_OFFSET supply transients must fall within specified voltages.

(3) Exceeding the recommended allowable absolute voltage difference between V_DDI and V_DD may result in excessive current draw and permanent damage to the device.

(4) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_OFFSET may result in excessive current draw and permanent damage to the device.

(5) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_RESET may result in excessive current draw and permanent damage to the device.

(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential inputs must not exceed the specified limit, or damage may result to the internal termination resistors.

(7) The highest temperature of the active array (as calculated in Section 6.6) or of any point along the window edge as defined in Figure 6-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 6-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.

(8) The temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge, as shown in Figure 6-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 6-1 are intended to result in the worst-case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.