DLPS258 Data sheet

DLPS258 August 2025 DLP472NP

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

FQY|174
- MCLG050

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

PARAMETER⁽⁷⁾		TEST CONDITIONS ⁽²⁾	MIN	MAX	UNIT
CURRENT
I_DD	Supply current: V_DD⁽³⁾⁽⁴⁾	Typical		140	mA
I_DDI	Supply current: V_DDI⁽³⁾⁽⁴⁾	Typical		45	mA
I_OFFSET	Supply current: V_OFFSET⁽⁵⁾⁽⁶⁾	Typical		6	mA
I_BIAS	Supply current: V_BIAS⁽⁵⁾⁽⁶⁾	Typical		.5	mA
I_RESET	Supply current: V_RESET⁽⁶⁾	Typical	-1.8		mA
POWER
P_DD	Supply power dissipation: V_DD⁽³⁾⁽⁴⁾	Typical		252	mW
P_DDI	Supply power dissipation: V_DDI⁽³⁾⁽⁴⁾	Typical		81	mW
P_OFFSET	Supply power dissipation: V_OFFSET⁽⁵⁾⁽⁶⁾	Typical		60	mW
P_BIAS	Supply power dissipation: V_BIAS⁽⁵⁾⁽⁶⁾	Typical		9	mW
P_RESET	Supply power dissipation: V_RESET⁽⁶⁾	Typical		25.2	mW
P_TOTAL	Supply power dissipation Total	Typical		427.2	mW
LPSDR INPUT
V_IH	High-level input voltage⁽⁸⁾⁽⁹⁾		0.7 x V_DD	V_DD + 0.3	x VDD
V_IL	Low-level input voltage⁽⁸⁾⁽⁹⁾		–0.3	0.3 x V_DD	x VDD
V_IH(AC)	AC input high voltage⁽⁸⁾⁽⁹⁾		0.8 × V_DD	V_DD + 0.3	x VDD
V_IL(AC)	AC input low voltage⁽⁸⁾⁽⁹⁾		–0.3	0.2 × V_DD	x VDD
VHyst	Input Hysteresis ( V_T+ – V_T– )		0.1 × V_DD	0.4 × V_DD	V
I_IL	Low level input current	V_DD = 1.95V, V_I = 0V	-100		nA
I_IH	High level input current	V_DD = 1.95V, V_I = 1.95V		135	uA
LPSDR OUTPUT
V_OH	DC output high voltage⁽¹⁰⁾	I_OH = –2mA	0.8 x V_DD		X VDD
V_OL	DC output low voltage⁽¹⁰⁾	I_OL = 2mA		0.2 x V_DD	X VDD
CAPACTIANCE
C_IN	Input capacitance LVCMOS	F = 1MHz		10	pF
C_IN	Input capacitance SubLVDS	F = 1MHz		20	pF
C_OUT	Output capacitance	F = 1MHz		10	pF

(1) Device electrical characteristics are over Section 5.4 unless otherwise noted.

(2) All voltage values are with respect to the ground pins (V_SS).

(3) To prevent excess current, the supply voltage delta | V_DDI – V_DD | must be less than the specified limit.

(4) Supply power dissipation based on non-compressed commands and data.

(5) To prevent excess current, the supply voltage delta | V_BIAS – V_OFFSET | must be less than the specified limit.

(6) Supply power dissipation based on three global resets in 200µs.

(7) All power supply connections are required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, V_RESET. All V_SS connections are also required.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) The low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR output specification is for pins LS_RDATA_A, LS_RDATA_B, LS_RDATA_C, LS_RDATA_D.