DLPS029F April 2013 – May 2019 DLPC350
The DMD interface is modeled after the low-power DDR-memory (LPDDR) interface. To minimize power dissipation, the LPDDR interface is defined to be unterminated. As a result, PCB signal-integrity management is imperative. Impedance control and crosstalk mitigation is critical to robust operation. LPDDR board design recommendations include trace spacing that is three times the trace width, impedance control within 10%, and signal routing directly over a neighboring reference plane (ground or 1.9-V plane).
DMD interface performance is also a function of trace length; therefore the length of the trace limits performance. The DLPC350 controller only works over a narrow range of DMD signal routing lengths at 120 MHz. Ensuring positive timing margins requires attention to many factors.
As an example, the DMD interface system timing margin can be calculated as follows.
PCB signal integrity degradation can be minimized by reducing the affects of simultaneously switching output (SSO) noise, crosstalk, and inter-symbol interface (ISI). Additionally, PCB routing mismatch can be budgeted via controlled PCB routing.
In an attempt to minimize the need for signal integrity analysis that would otherwise be required, the following PCB design guidelines are provided. They describe an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements.