DLPS029F April 2013 – May 2019 DLPC350
Although the DLPC350 controller requires an array of power supply voltages, (for example, VDDC, VDD_1X_PLLX, VCC_18, VCC_DMD, and VCCXX_FPD), there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC350 controller. This is true for both power-up and power-down. Similarly, there is no minimum time between powering-up or powering-down the different supplies of the DLPC350 controller. Note that it is not uncommon for there to be power-sequencing requirements for other devices that share power supplies with the DLPC350 controller.
Although there is no risk of damaging the DLPC350 controller as a result of a given power sequence, from a functional standpoint there are a few specific power-sequencing recommendations to ensure proper operation.
It is assumed that all DLPC350 power-up sequencing is handled by external hardware. It is also assumed that an external power monitor will hold the DLPC350 controller in system reset during power-up (that is, POSENSE = 0). It should continue to assert system reset until all DLPC350 voltages have reached minimum specified voltage levels. During this time, all controller I/O are either 3-stated or driven low. The master PLL (PLLM) is released from reset upon the low-to-high transition of POSENSE, but the DLPC350 controller keeps the rest of the controller in reset for an additional 100 ms to allow the PLL to lock and stabilize its outputs. After this 100-ms delay, internal resets are de-asserted causing the microprocessor to begin its boot-up routine.