6.6 I2C0 and I2C1 Interface Timing Requirements(1)(2)(3)
||Clock frequency, HOST_I2C_SCL
(50% reference points)
(1) Meets I2C timing per the I2C Bus Specification, unless otherwise noted. For reference see version 2.1 of the Phillips/NXP specification.
(2) The maximum clock frequency does not account for rise time, nor added capacitance of PCB or external components which may adversely impact this value.
(3) By definition, I2C transactions operate at the speed of the slowest device on the bus and thus there is no requirement to match the speed grade of all devices in the system. However if Full-speed operation is desired, it will be necessary to ensure the other I2C devices support full-speed operation as well. In addition to other devices slowing down bus operation, the length of the line (due to its capacitance) and the value of the I2C pullup resistors will also influence the max achievable speed.
The data setup time should be greater than 300 ns. This differs from the I2