DLPS029F April 2013 – May 2019 DLPC350
The data interface has two components: a parallel RGB-input port and an FPD-Link LVDS input port. Both components can support up to 30 bits and have a nominal I/O voltage of 3.3 V. The Interface Timing Requirements in Specifications list the maximum and minimum input timing specifications for both components.
The parallel RGB port can support up to 30 bits in video mode. In pattern mode, the upper 8-bits of each color convert the 30-bit input into a 24-bit RGB input.
The FPD-Link input port can be configured to connect to a video decoder device or an external processor through a 24-, 27-, or 30-bit interface.
Table 11 provides a description of the signals associated with the data interface.
|RGB Parallel Interface|
|P1_(A, B, C)_[0:9]||30-bit data inputs 10 bits for each of the red, green, and blue channels). If interfacing to a system with less than 10-bits per color, connect the bus of the red, green, and blue channels to the upper bits of the DLPC350 10-bit bus.|
|P1A_CLK||Pixel clock; all input signals on data interface are synchronized with this clock.|
|P1_DATAEN||Input data valid|
|FPD-Link LVDS Input|
|RCK||Differential input signal for clock|
|RA_IN||Differential input signal for data channel A|
|RB_IN||Differential input signal for data channel B|
|RC_IN||Differential input signal for data channel C|
|RD_IN||Differential input signal for data channel D|
|RE_IN||Differential input signal for data channel E|
The A, B, and C input data channels of Port 1 can be internally swapped for optimum board layout.