DLPS029F April 2013 – May 2019 DLPC350
In order to meet the specifications listed in the following tables, typically the PCB designer must route these signals manually (not using automated PCB routing software). In case of length matching requirements, routing traces in a serpentine fashion may be required. Keep the number of turns to a minimum and the turn angles no sharper than 45°. Traces must be 0.1 inches from board edges when possible; otherwise they must be 0.05 inches minimum from the board edges. Avoid routing long traces all around the PCB. PCB layout assumes adjacent trace spacing is twice the trace width. However, three times the trace width will reduce crosstalk and significantly help performance.
The maximum and minimum signal routing trace lengths include escape routing.
|SIGNALS||MINIMUM SIGNAL ROUTING LENGTH(1)||MAXIMUM SIGNAL ROUTING LENGTH(2)|
|DMD_D(23:0), DMD_DCLK, DMD_TRC, DMD_SCTRL, DMD_LOADB,||2480 mil
|DMD_OE, DMD_DRC_STRB, DMD_DRC_BUS, DMD_SAC_CLK, and DMD_SAC_BUS||512 mil
Each high-speed, single-ended signal should be routed in relation to its reference signal, such that a constant impedance is maintained throughout the routed trace. Avoid sharp turns and layer switching while keeping total trace lengths to a minimum. The following signals should follow the signal matching requirements described in Table 21.
|SIGNALS||REFERENCE SIGNAL||MAX MISMATCH||UNIT|
|DMD_D(23:0), DMD_TRC, DMD_SCTRL, DMD_LOADB||DMD_DCLK||±200
|DMD_DRC_STRB, DMD_DRC_BUS, DMD_SAC_BUS, DMD_OE||DMD_SAC_CLK||±200
The values in Table 21 apply to the PCB routing only. They do not include any internal package routing mismatch associated with the DLPC350 or DMD. Additional margin can be attained if internal DLPC350 package skew is taken into account. Additionally, to minimize EMI radiation, serpentine routes added to facilitate trace length matching should only be implemented on signal layers between reference planes.
Both the DLPC350 output timing parameters and the DMD input timing parameters include a timing budget to account for their respective internal package routing skew. Thus, additional system margin can be attained by comprehending the package variations and compensating for them in the PCB layout. To increase the system timing margin, TI recommends that the DLPC350 package variation be compensated for (by signal group), but it may not be desirable to compensate for DMD package skew. This is due to the fact that each DMD has a different skew profile, making the PCB layout DMD specific. To use a common PCB design for different DMDs, TI recommends that either the DMD package skew variation not be compensated for on the PCB, or the package lengths for all applicable DMDs being considered. Table 22 provides the DLPC350 package output delay at the package ball for each DMD interface signal.
The total length of all the traces in Table 22 should be matched to the DMD_DCLK trace length. Total trace length includes package skews, PCB length, and DMD flex cable length.
|SIGNAL||TOTAL DELAY (Package Skews)||PACKAGE PIN|
|SIGNAL||ROUTING PRIORITY||ROUTING LAYER||MATCHING REFERENCE SIGNAL||TOLERANCE|
|DMD_D[23:0], DMD_SCTRL, DMD_TRC, DMD_LOADB(1)(2)(3)(4)||1||3, 4||DMD_DCLK||±150 mils|
|P1_A[9:0], P1_B[9:0], P1_C[9:0], P1_HSYNC, P1_VSYNC, P1_DATAEN, P1X_CLK||1||3, 4||P1X_CLK||±0.1 inches|
|R[A-E]_IN_P, R[A-E]_IN_N, RCK_IN_P, RCK_IN_N||2||3, 4||RCK||±150 mils
Differential signals need to be matched within ±12 mils