DLPS074 February 2017 DLPC4422
The DLPC4422 controller provides three external program memory chip selects:
Flash and SRAM access timing is software programmable up to 31 wait states. Wait state resolution is 6.7 ns in normal mode and 53.33 ns in low power modes. Wait state program values for typical flash access times are shown in the Table 4.
|Normal Mode (1)||Low Power Mode(1)|
|Formula to Calculate the Required Wait State Value||= Roundup (Device_Access_Time / 6.7 ns)||= Roundup (Device_Access_Time / 53.33 ns)|
|Max Supported Device Access Time||207 ns||1660 ns|
Note that when another device such as an SRAM or additional flash is used in conjunction with the boot flash, care must be taken to keep stub length short and located as close as possible to the flash end of the route.
The DLPC4422 controller provides enough Program Memory Address pins to support a flash or SRAM device up to 128 Mb. For systems not requiring this capacity, up to two address pins can be used as GPIO instead. Specifically, the two most significant address bits (i.e. PM_ADDR_22 and PM_ADDR_21) are shared on pins GPIO_36 and GPIO_35 respectively. Like other GPIO pins, these pins float in a high-impedance input state following reset; therefore, if these GPIO pins are to be reconfigured as Program Memory Address pins, they require board-level pull-down resistors to prevent any flash address bits from floating until software is able to reconfigure the pins from GPIO to Program Memory Address. Also note that until software reconfigures the pins from GPIO to Program Memory Address, upper portions of flash memory are not accessible.
Table 5 shows typical GPIO_35 and GPIO36 pin configuration for various flash sizes.