10.1.3 DMD Interface Considerations

The DMD interface is modeled after the low-power DDR memory (LPDDR) interface. To minimize power dissipation, the LPDDR interface is defined to be unterminated. This makes good PCB signal integrity management imperative. In particular, impedance control and crosstalk mitigation is critical to robust operation. LPDDR board design recommendations include 3× design rules (that is, trace spacing = 3× trace width), ±10% impedance control, and signal routing directly over a neighboring reference plane (ground or 1.9-V plane).

DMD interface performance is also a function of trace length, so even with good board design, the length of the line limits performance. The DLPC6401 device works over a very-narrow range of DMD signal routing lengths at 120 MHz only. The device provides the option to reduce the interface clock rate to facilitate a longer interface (this includes 106.7-MHz, 96-MHz, 87.7-MHz, and 80-MHz programming options). However, note that reducing the interface clock rate has the impact of increasing DMD load time, which in turn reduces image quality. Even with a clock reduction, the edge rates required to achieve the fastest clock rates still exist and cause overshoot and undershoot issues if there is excessive crosstalk, or the line is too short. Thus, ensuring positive timing margin requires attention to many factors.

As an example, DMD interface system timing margin can be calculated as follows:

Where PCB SI degradation is signal integrity degradation due to PCB effects, which include simultaneously switching output (SSO) noise, crosstalk, and inter-symbol interference (ISI). The DLPC6401 I/O timing parameters can be found in their corresponding tables. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI degradation is not so straightforward.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements.

PCB design:
	●	Configuration:	Asymmetric dual stripline
	●	Signal routing layer thickness (T):	1.0-oz copper (1.2 mil)
	●	Single-ended signal impedance controlled:	50 Ω (±10%)
	●	Differential signal impedance controlled:	100-Ω differential (±10%)
PCB Stackup:
	●	Reference plane 1 is assumed to be a ground plane for proper return path.
	●	Reference plane 2 is assumed to be the 1.9-V DMD I/O power plane or another ground plane.
	●	Dielectric FR4, (Er):	4.3 at 1 GHz (nominal)
	●	Signal trace distance to reference plane 1 (H1):	5 mil (nominal)
	●	Signal trace distance to reference plane 2 (H2):	30.4 mil (nominal)
	●	If additional routing layers are required, ensure they are adjacent to one of these reference planes
Figure 19. PCB Stackup Geometries
Flex design:
	●	Configuration:	2-layer microstrip
	●	The reference plane is assumed to be a ground plane for proper return path.
	●	Vias:	Max 2 per signal
	●	Single trace width:	4 mil (min)
	●	Signal routing layer thickness (T):	0.5-oz copper (0.6 mil)
	●	Single-ended signal impedance controlled:	50 Ω (±10%)

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• Number of layer changes:
  • Minimize layer changes
• Stubs:
  • Stubs should be avoided

However, note that both the DLPC6401 output timing parameters and the DMD input timing parameters include timing budget to account for their respective internal package routing skew. Thus, additional system margin can be attained by comprehending the package variations and compensating for them in the PCB layout. To increase system timing margin, TI recommends that DLPC6401 package variation be compensated for (by signal group), but it may not be desirable to compensate for DMD package skew. Because, each DMD has a different skew profile making the PCB layout DMD specific. Thus, if an OEM wants to use a common PCB design for different DMDs, TI recommends that either the DMD package skew variation not be compensated for on the PCB or the package lengths for all applicable DMDs be considered. Table 14 provides the DLPC6401 package output delay at the package ball for each DMD I/F signal. DMD internal routing skew data is contained in the DMD data sheet.