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DLPC6401

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DLP® display controller for high-brightness portable displays

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Data sheet

DLPC6401

ACTIVE
Data sheet Order now

Product details

Component type Display Controller Chipset family DLP4500, DLPC6401 Display resolution (max) WXGA (1280x800) Operating temperature range (°C) 0 to 55 Rating Catalog
Component type Display Controller Chipset family DLP4500, DLPC6401 Display resolution (max) WXGA (1280x800) Operating temperature range (°C) 0 to 55 Rating Catalog
PBGA (ZFF) 419 529 mm² 23 x 23
  • Provides a 30-Bit Input Pixel Interface:
    • YUV, YCrCb, or RGB Data Format
    • 8, 9, or 10 Bits per Color
    • Pixel Clock Support up to 150 MHz
  • Provides a Single Channel, LVDS Based,
    Flat-Panel Display (FPD)-Link Compatible Input Interface:
    • Supports Sources up to a 90-MHz Effective Pixel Clock Rate
    • Four Demodulated Pixel-Mapped Modes Supported for 8, 9, 10 YUV, YCrCb, or RGB Formatted Inputs
  • Supports 45- to 120-Hz Frame Rates
  • Full Support for Diamond 0.45 WXGA
  • High-Speed, Double Data Rate (DDR) Digital Micromirror Device (DMD) Interface
  • 149.33-MHz ARM926™ Microprocessor
  • Microprocessor Peripherals:
    • Programmable Pulse-Width Modulation (PWM) and Capture Timers
    • Two I2C Ports
    • Two UART Ports (for Debug Only)
    • 32 KB of Internal RAM
    • Dedicated LED PWM Generators
  • Image Processing:
    • Auto-Lock for Standard, Wide, and Black Border
    • 1D Keystone Correction
    • Programmable Degamma
  • On-Screen Display (OSD)
  • Splash Screen Display Support
  • Integrated Clock Generation Circuitry
    • Operates on a Single 32-MHz Crystal
    • Integrated Spread Spectrum Clocking
  • Integrated 64-Mb Frame Memory Eliminates the Need for External High-Speed Memory
  • External Memory Support: Parallel Flash for Microprocessor and PWM Sequence
  • System Control:
    • DMD Power and Reset Driver Control
    • DMD Horizontal and Vertical Image Flip
  • JTAG Boundary Scan Test Support
  • 419-Pin Plastic Ball Grid Array Package
  • Provides a 30-Bit Input Pixel Interface:
    • YUV, YCrCb, or RGB Data Format
    • 8, 9, or 10 Bits per Color
    • Pixel Clock Support up to 150 MHz
  • Provides a Single Channel, LVDS Based,
    Flat-Panel Display (FPD)-Link Compatible Input Interface:
    • Supports Sources up to a 90-MHz Effective Pixel Clock Rate
    • Four Demodulated Pixel-Mapped Modes Supported for 8, 9, 10 YUV, YCrCb, or RGB Formatted Inputs
  • Supports 45- to 120-Hz Frame Rates
  • Full Support for Diamond 0.45 WXGA
  • High-Speed, Double Data Rate (DDR) Digital Micromirror Device (DMD) Interface
  • 149.33-MHz ARM926™ Microprocessor
  • Microprocessor Peripherals:
    • Programmable Pulse-Width Modulation (PWM) and Capture Timers
    • Two I2C Ports
    • Two UART Ports (for Debug Only)
    • 32 KB of Internal RAM
    • Dedicated LED PWM Generators
  • Image Processing:
    • Auto-Lock for Standard, Wide, and Black Border
    • 1D Keystone Correction
    • Programmable Degamma
  • On-Screen Display (OSD)
  • Splash Screen Display Support
  • Integrated Clock Generation Circuitry
    • Operates on a Single 32-MHz Crystal
    • Integrated Spread Spectrum Clocking
  • Integrated 64-Mb Frame Memory Eliminates the Need for External High-Speed Memory
  • External Memory Support: Parallel Flash for Microprocessor and PWM Sequence
  • System Control:
    • DMD Power and Reset Driver Control
    • DMD Horizontal and Vertical Image Flip
  • JTAG Boundary Scan Test Support
  • 419-Pin Plastic Ball Grid Array Package

The DLPC6401 digital controller, part of the DLP4500 (.45 WXGA) chipset, supports reliable operation of the DLP4500 digital micromirror device (DMD). The DLPC6401 controller provides a convenient, multi-functional interface between system electronics and the DMD, enabling small form factor and high resolution HD displays.

The DLPC6401 digital controller, part of the DLP4500 (.45 WXGA) chipset, supports reliable operation of the DLP4500 digital micromirror device (DMD). The DLPC6401 controller provides a convenient, multi-functional interface between system electronics and the DMD, enabling small form factor and high resolution HD displays.

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet DLPC6401 DLP® Data Processor datasheet (Rev. C) PDF | HTML 11 Aug 2015
White paper DLP Technology for Mobile Smart TV (Rev. D) 11 Jun 2024
Application note TI DLP® 디스플레이 기술 시작하기 (Rev. H) PDF | HTML 03 May 2024
Application note 開始使用 TI DLP® 顯示技術 (Rev. H) PDF | HTML 03 May 2024
Application note Getting Started With TI DLP® Display Technology (Rev. H) PDF | HTML 18 Apr 2024
Application note DLP System Design: Brightness Requirements and Tradeoffs (Rev. C) PDF | HTML 05 May 2022
White paper TI DLP® Pico™ Technology for smart home applications (Rev. B) 08 Feb 2019
User guide DLPC6401 Formatter-Only Software Programmer’s User's Guide (Rev. A) 31 Jan 2019
Application note DLP Pico Discrete LED driver design guide & LM3434 Application Note (Rev. A) 15 Mar 2016
Application note TI DLP® IntelliBright™ Algorithms for the DLPC343x Controller 08 Dec 2014
User guide DLPC6401 GUI User’s Guide 30 Dec 2013

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