Product details

Chipset family DLP4500, DLPC6401 Component type Display Controller Display resolution (Max) WXGA (1280x800) Input frame rate (Max) (Hz) 120 Video ports 30-bit RGB, BT656, LVDS, Parallel
Chipset family DLP4500, DLPC6401 Component type Display Controller Display resolution (Max) WXGA (1280x800) Input frame rate (Max) (Hz) 120 Video ports 30-bit RGB, BT656, LVDS, Parallel
BGA (ZFF) 419 529 mm² 23 x 23
  • Provides a 30-Bit Input Pixel Interface:
    • YUV, YCrCb, or RGB Data Format
    • 8, 9, or 10 Bits per Color
    • Pixel Clock Support up to 150 MHz
  • Provides a Single Channel, LVDS Based,
    Flat-Panel Display (FPD)-Link Compatible Input Interface:
    • Supports Sources up to a 90-MHz Effective Pixel Clock Rate
    • Four Demodulated Pixel-Mapped Modes Supported for 8, 9, 10 YUV, YCrCb, or RGB Formatted Inputs
  • Supports 45- to 120-Hz Frame Rates
  • Full Support for Diamond 0.45 WXGA
  • High-Speed, Double Data Rate (DDR) Digital Micromirror Device (DMD) Interface
  • 149.33-MHz ARM926™ Microprocessor
  • Microprocessor Peripherals:
    • Programmable Pulse-Width Modulation (PWM) and Capture Timers
    • Two I2C Ports
    • Two UART Ports (for Debug Only)
    • 32 KB of Internal RAM
    • Dedicated LED PWM Generators
  • Image Processing:
    • Auto-Lock for Standard, Wide, and Black Border
    • 1D Keystone Correction
    • Programmable Degamma
  • On-Screen Display (OSD)
  • Splash Screen Display Support
  • Integrated Clock Generation Circuitry
    • Operates on a Single 32-MHz Crystal
    • Integrated Spread Spectrum Clocking
  • Integrated 64-Mb Frame Memory Eliminates the Need for External High-Speed Memory
  • External Memory Support: Parallel Flash for Microprocessor and PWM Sequence
  • System Control:
    • DMD Power and Reset Driver Control
    • DMD Horizontal and Vertical Image Flip
  • JTAG Boundary Scan Test Support
  • 419-Pin Plastic Ball Grid Array Package
  • Provides a 30-Bit Input Pixel Interface:
    • YUV, YCrCb, or RGB Data Format
    • 8, 9, or 10 Bits per Color
    • Pixel Clock Support up to 150 MHz
  • Provides a Single Channel, LVDS Based,
    Flat-Panel Display (FPD)-Link Compatible Input Interface:
    • Supports Sources up to a 90-MHz Effective Pixel Clock Rate
    • Four Demodulated Pixel-Mapped Modes Supported for 8, 9, 10 YUV, YCrCb, or RGB Formatted Inputs
  • Supports 45- to 120-Hz Frame Rates
  • Full Support for Diamond 0.45 WXGA
  • High-Speed, Double Data Rate (DDR) Digital Micromirror Device (DMD) Interface
  • 149.33-MHz ARM926™ Microprocessor
  • Microprocessor Peripherals:
    • Programmable Pulse-Width Modulation (PWM) and Capture Timers
    • Two I2C Ports
    • Two UART Ports (for Debug Only)
    • 32 KB of Internal RAM
    • Dedicated LED PWM Generators
  • Image Processing:
    • Auto-Lock for Standard, Wide, and Black Border
    • 1D Keystone Correction
    • Programmable Degamma
  • On-Screen Display (OSD)
  • Splash Screen Display Support
  • Integrated Clock Generation Circuitry
    • Operates on a Single 32-MHz Crystal
    • Integrated Spread Spectrum Clocking
  • Integrated 64-Mb Frame Memory Eliminates the Need for External High-Speed Memory
  • External Memory Support: Parallel Flash for Microprocessor and PWM Sequence
  • System Control:
    • DMD Power and Reset Driver Control
    • DMD Horizontal and Vertical Image Flip
  • JTAG Boundary Scan Test Support
  • 419-Pin Plastic Ball Grid Array Package

The DLPC6401 digital controller, part of the DLP4500 (.45 WXGA) chipset, supports reliable operation of the DLP4500 digital micromirror device (DMD). The DLPC6401 controller provides a convenient, multi-functional interface between system electronics and the DMD, enabling small form factor and high resolution HD displays.

The DLPC6401 digital controller, part of the DLP4500 (.45 WXGA) chipset, supports reliable operation of the DLP4500 digital micromirror device (DMD). The DLPC6401 controller provides a convenient, multi-functional interface between system electronics and the DMD, enabling small form factor and high resolution HD displays.

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Technical documentation

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Type Title Date
* Data sheet DLPC6401 DLP® Data Processor datasheet (Rev. C) 11 Aug 2015
Application note TI DLP® 디스플레이 기술 시작하기 (Rev. E) 02 Dec 2021
Application note 開始使用 TI DLP® 顯示技術 (Rev. E) 02 Dec 2021
Application note Getting Started with TI DLP® Display Technology (Rev. E) 03 Aug 2021
Application note DLP System Design: Brightness Requirements and Tradeoffs (Rev. B) 13 Nov 2019
White paper TI DLP® Pico™ Technology for smart home applications (Rev. B) 08 Feb 2019
User guide DLPC6401 Formatter-Only Software Programmer’s User's Guide (Rev. A) 31 Jan 2019
Application note DLP Pico Discrete LED driver design guide & LM3434 Application Note (Rev. A) 15 Mar 2016
White paper DLP Pico Technology for Screenless Display (Rev. B) 12 Jan 2016
Application note TI DLP® IntelliBright™ Algorithms for the DLPC343x Controller 08 Dec 2014
User guide DLPC6401 GUI User’s Guide 30 Dec 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DLPC6401DISPLAYEVM — DLPC6401-based DLP® Display EVM

This evaluation module (EVM) contains TI's 0.45WXGA chipset (DLP4501 and DLPC6401) designed for data and video display applications. The EVM offers a compelling combination of resolution, brightness, and programmability.

The S8 EVM is available through a third party partner, Anuha.

Included with the (...)

GUI for evaluation module (EVM)

DLPC6401 GUI Files

DLPC139.ZIP (4421 KB)
Simulation model

DLPC6401 IBIS Model

DLPM023.ZIP (109 KB) - IBIS Model
Reference designs

TIDA-00782 — Portable, High Brightness HD Projection Display Reference Design using DLP® Technology

This reference design, featuring the DLP Pico™ 0.45-inch WXGA display chipset enables use of HD resolution for projection display applications such as accessory projectors, smart projectors, mobile Smart TV, built in projectors like projection functionality inside notebooks, laptops and hot (...)
Package Pins Download
BGA (ZFF) 419 View options

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