SNLS638B December   2018  – January 2025 DP83825I

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     DP83825I Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Auto-Negotiation (Speed / Duplex Selection)
      2. 6.3.2  Auto-MDIX Resolution
      3. 6.3.3  Energy Efficient Ethernet
        1. 6.3.3.1 EEE Overview
        2. 6.3.3.2 EEE Negotiation
      4. 6.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 6.3.5  Wake-on-LAN Packet Detection
        1. 6.3.5.1 Magic Packet Structure
        2. 6.3.5.2 Magic Packet Example
        3. 6.3.5.3 Wake-on-LAN Configuration and Status
      6. 6.3.6  Low Power Modes
        1. 6.3.6.1 Active Sleep
      7. 6.3.7  IEEE Power Down
      8. 6.3.8  Deep Power Down
      9. 6.3.9  Reduced Media Independent Interface (RMII)
      10. 6.3.10 RMII Repeater Mode
      11. 6.3.11 Serial Management Interface
        1. 6.3.11.1 Extended Register Space Access
        2. 6.3.11.2 Read Operation
        3. 6.3.11.3 Write Operation
      12. 6.3.12 100BASE-TX
        1. 6.3.12.1 100BASE-TX Transmitter
          1. 6.3.12.1.1 Code-Group Encoding and Injection
          2. 6.3.12.1.2 Scrambler
          3. 6.3.12.1.3 NRZ to NRZI Encoder
          4. 6.3.12.1.4 Binary to MLT-3 Converter
        2. 6.3.12.2 100BASE-TX Receiver
      13. 6.3.13 10BASE-Te
        1. 6.3.13.1 Squelch
        2. 6.3.13.2 Normal Link Pulse Detection and Generation
        3. 6.3.13.3 Jabber
        4. 6.3.13.4 Active Link Polarity Detection and Correction
      14. 6.3.14 Loopback Modes
        1. 6.3.14.1 MII Loopback
        2. 6.3.14.2 PCS Loopback
        3. 6.3.14.3 Digital Loopback
        4. 6.3.14.4 Analog Loopback
        5. 6.3.14.5 Reverse Loopback
      15. 6.3.15 BIST Configurations
      16. 6.3.16 Cable Diagnostics
        1. 6.3.16.1 TDR
        2. 6.3.16.2 Fast Link-Drop Functionality
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Straps Configuration
        1. 6.5.1.1 Straps for PHY Address
    6. 6.6 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Clock Requirements
          1. 7.2.1.1.1 Oscillator
          2. 7.2.1.1.2 Crystal
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 RMII Layout Guidelines
        2. 7.2.2.2 MDI Layout Guidelines
        3. 7.2.2.3 TPI Network Circuit
        4. 7.2.2.4 VOD Configuration
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Signal Traces
        2. 7.4.1.2 Return Path
        3. 7.4.1.3 Transformer Layout
          1. 7.4.1.3.1 Transformer Recommendations
        4. 7.4.1.4 Capacitive DC Blocking
        5. 7.4.1.5 Metal Pour
        6. 7.4.1.6 PCB Layer Stacking
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.13.1 Squelch

Squelch is responsible for determining when valid data is present on the differential receive inputs. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10BASE-Te standard) to determine the validity of data on the twisted-pair inputs.

The signal at the start of a packet is checked by the squelch, and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) are rejected. When this first squelch level is exceeded correctly, the opposite squelch level must then be exceeded no earlier than 50ns. Finally, the signal must again exceed the original squelch level no earlier than 50ns to qualify as a valid input waveform, and not be rejected. This checking procedure results in the typical loss of three preamble bits at the beginning of each packet. When the transmitter is operating, five consecutive transitions are checked before indicating that valid data is present. At this time, the squelch circuitry is reset.