SNLS638B December 2018 – January 2025 DP83825I
PRODUCTION DATA
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| TX_EN | 1 | Reset: I, PD Active: I, PD |
RMII Transmit Enable: TX_EN is active high signal and is presented on the rising edge of the TX_CLK. TX_EN indicates the presence of valid data inputs on TX_D [1:0]. |
| 50MHzOut/LED2 | 2 | Reset: I, PD, S Active: O |
RMII Master Mode: 50MHz Clock Out(default). RMII Slave Mode: LED_2(default). This pin can be configured as GPIO using register configuration. |
| INTR/PWRDN | 3 | Reset: I, PU Active: I/O, PU |
Interrupt / Power Down(default): The default function of this pin is power down. Register access is required to configure this pin as an interrupt. In power-down function, an active low signal on this pin places the device in power down mode. When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup (9.5kΩ). Some applications can require an external pullup resistor. |
| LED0 | 4 | Reset: I, PD, S Active: O |
LED0 : Activity Indication LED
indicates transmit and receive activity in addition to the status of the Link. The
LED is ON when Link is good. The LED blinks when the transmitter or receiver is
active. This pin can also act as GPIO through register configuration. This pin is at 3.3V always and not linked to voltage supplied to VDDIO pin. This is to avoid external components when operating PHY at VDDIO 1.8V. |
| RST_N | 5 | Reset: I, PU Active: I, PU |
RST_N: This pin is an active low
reset input. Asserting this pin low for at least 25μs forces a reset process to
occur. Initiation of reset causes strap pins to be re-scanned and resets all the
internal registers of the PHY to default value. This pin is at 3.3V always and not linked to voltage supplied to VDDIO pin. This is to avoid external components when operating PHY at VDDIO 1.8V. |
| VDDA3V3 | 6 | Power | Input Analog Supply: 3.3V. For decoupling capacitor requirements, refer to the Section 7.3 section. |
| RD_M | 7 | A | Differential Receive Input (PMD): These differential inputs are automatically configured to accept either 10BASE-Te, 100BASE-TX specific signaling mode |
| RD_P | 8 | A | |
| GND | 9 | GND | Ground: Connect to Ground |
| TD_M | 10 | A | Differential Transmit Output (PMD): These differential outputs are configured to either 10BASE-Te, 100BASE-TX signaling mode based on configuration chosen for PHY. |
| TD_P | 11 | A | |
| XO | 12 | A | Crystal Output: Reference Clock output. XO pin is used for crystal only. This pin can be left floating when a CMOS-level oscillator is connected to XI. |
| XI/50MHzIn | 13 | A | Crystal / Oscillator Input Clock RMII Master mode: 25MHz ±50ppm-tolerance crystal or oscillator clock RMII Slave mode: 50MHz ±50ppm-tolerance CMOS-level oscillator clock |
| RBIAS | 14 | A | This pin needs a biasing resistor. Connect a 6.49kΩ ±1% tolerance resistor between RBIAS pin and ground. |
| MDIO | 15 | Reset: I, PU-10kΩ Active: I/O, PU-10kΩ |
Management Data I/O: Bidirectional management data signal that can be source by the management station or the PHY. This pin has internal pullup of 10kΩ. External pullup of up to 2.2kΩ can be added if needed |
| MDC | 16 | Reset: I, PD Active: I, PD |
Management Data Clock: Synchronous clock to the MDIO serial management input/output data. This clock can be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 24MHz. There is no minimum clock rate. |
| RX_D1 | 17 | Reset: I, PD, S Active: O |
RMII Receive Data: Symbols received on the cable are decoded and presented on these pins synchronous to reference clock. These symbols contain valid data when RX_DV is asserted. |
| RX_D0 | 18 | Reset: I, PD, S Active: O |
RMII Receive Data: Symbols received on the cable are decoded and presented on these pins synchronous to reference clock. These symbols contain valid data when RX_DV is asserted. |
| VDDIO | 19 | Power | I/O Supply : 3.3V/1.8V. For decoupling capacitor requirements, refer to the Section 7 section. |
| CRS_DV | 20 | Reset: I, PD, S Active: O |
Carrier Sense / Receive Data Valid: This pin combines the RMII Carrier and Receive Data Valid indications. |
| GND | 21 | GND | Ground pin |
| RX_ER | 22 | Reset: I, PD, S Active: O |
RMII Receive Error: This pin indicates an error symbol has been detected within a received packet in RMII mode. RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required by the MAC in RMII mode, because the PHY automatically corrupts data on a receive error. |
| TX_D0 | 23 | Reset: I, PD Active: I, PD |
RMII Transmit Data: TX_D[1:0] received from the MAC is synchronous to the rising edge of the reference clock. |
| TX_D1 | 24 | Reset: I, PD Active: I, PD |
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