Refer to the PDF data sheet for device specific package drawings
Table 7-17 shows the stackup and feature sizes required for these types of PCIe connections.
|Number of ground plane cuts allowed within PCIe routing region||-||-||0||Cuts|
|Number of layers between PCIe routing area and reference plane (1)||-||-||0||Layers|
|PCB Routing clearance||4||Mils|
|PCB Trace width||4||Mils|