Refer to the PDF data sheet for device specific package drawings
TPS65919 or LP8733 are the Power Management ICs (PMICs) that should be used for the Device designs. TI requires use of these PMICs for the following reasons:
Whenever one SMPS supplies multiple SoC voltage domains from a common power rail, the most stringent PDN guideline across the voltage domains being combined should be applied to the common power rail.
It is possible that some voltage domains on the device are unused in some systems. In such cases, to ensure device reliability, it is still required that the supply pins for the specific voltage domains are connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the system. e.g. if the DSP domain is not used, it can be combined with the CORE domain, thereby having a single power supply driving the combined CORE and DSP domains.
For the combined rail, the following relaxations do apply:
Table 7-4 illustrates the approved and validated power supply connections to the Device for the SMPS outputs of the TPS656919 PMIC.
|SMPS||Valid Combination||TPS65919 Current Limitation(2)(3)|
|SMPS2||Free (DDR Memory)||3.5A|
Table 7-5 illustrates the approved and validated power supply connections to the Device for the SMPS outputs of the LP8733 PMIC.
|SMPS||Valid Combination||LP8733 Current Limitation(1)(2)|