Refer to the PDF data sheet for device specific package drawings
The device Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) consists of dual 32-bit Load / Store RISC CPU cores - Programmable Real-Time Units (PRU0 and PRU1), shared, data, and instruction memories, internal peripheral modules, and an interrupt controller (PRU-ICSS_INTC). The programmable nature of the PRUs, along with their access to pins, events and all SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, customer peripheral interfaces, and in off-loading tasks from the other processor cores of the system-on-chip (SoC).
The each PRU-ICSS includes the following main features:
For more information, see chapter Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) of the device TRM.