SLVSFJ1C November   2021  – August 2022 DRV8245-Q1

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 HW Variant
      1. 6.1.1 HTSSOP (28) Package
      2. 6.1.2 VQFN-HR(16) Package
    2. 6.2 SPI Variant
      1. 6.2.1 HTSSOP (28) Package
      2. 6.2.2 VQFN-HR (16) Package
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
      1. 7.5.1  Power Supply & Initialization
      2. 7.5.2  Logic I/Os
      3. 7.5.3  SPI I/Os
      4. 7.5.4  Configuration Pins - HW Variant Only
      5. 7.5.5  Power FET Parameters
      6. 7.5.6  Switching Parameters with High-Side Recirculation
      7. 7.5.7  Switching Parameters with Low-Side Recirculation
      8. 7.5.8  IPROPI & ITRIP Regulation
      9. 7.5.9  Over Current Protection (OCP)
      10. 7.5.10 Over Temperature Protection (TSD)
      11. 7.5.11 Voltage Monitoring
      12. 7.5.12 Load Monitoring
      13. 7.5.13 Fault Retry Setting
      14. 7.5.14 Transient Thermal Impedance & Current Capability
    6. 7.6 SPI Timing Requirements
    7. 7.7 Switching Waveforms
      1. 7.7.1 Output switching transients
        1. 7.7.1.1 High-Side Recirculation
        2. 7.7.1.2 Low-Side Recirculation
      2. 7.7.2 Wake-up Transients
        1. 7.7.2.1 HW Variant
        2. 7.7.2.2 SPI Variant
      3. 7.7.3 Fault Reaction Transients
        1. 7.7.3.1 Retry setting
        2. 7.7.3.2 Latch setting
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 HW Variant
      2. 8.2.2 SPI Variant
    3. 8.3 Feature Description
      1. 8.3.1 External Components
        1. 8.3.1.1 HW Variant
        2. 8.3.1.2 SPI Variant
      2. 8.3.2 Bridge Control
        1. 8.3.2.1 PH/EN mode
        2. 8.3.2.2 PWM mode
        3. 8.3.2.3 Independent mode
        4. 8.3.2.4 Register - Pin Control - SPI Variant Only
      3. 8.3.3 Device Configuration
        1. 8.3.3.1 Slew Rate (SR)
        2. 8.3.3.2 IPROPI
        3. 8.3.3.3 ITRIP Regulation
        4. 8.3.3.4 DIAG
          1. 8.3.3.4.1 HW variant
          2. 8.3.3.4.2 SPI variant
      4. 8.3.4 Protection and Diagnostics
        1. 8.3.4.1 Over Current Protection (OCP)
        2. 8.3.4.2 Over Temperature Protection (TSD)
        3. 8.3.4.3 Off-State Diagnostics (OLP)
        4. 8.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 8.3.4.5 VM Over Voltage Monitor
        6. 8.3.4.6 VM Under Voltage Monitor
        7. 8.3.4.7 Power On Reset (POR)
        8. 8.3.4.8 Event Priority
    4. 8.4 Device Functional States
      1. 8.4.1 SLEEP State
      2. 8.4.2 STANDBY State
      3. 8.4.3 Wake-up to STANDBY State
      4. 8.4.4 ACTIVE State
      5. 8.4.5 nSLEEP Reset Pulse (HW Variant Only)
    5. 8.5 Programming - SPI Variant Only
      1. 8.5.1 SPI Interface
      2. 8.5.2 Standard Frame
      3. 8.5.3 SPI Interface for Multiple Peripherals
        1. 8.5.3.1 Daisy Chain Frame for Multiple Peripherals
    6. 8.6 Register Map - SPI Variant Only
      1. 8.6.1 User Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.1 Output switching transients

This section illustrates the switching transients for an inductive load due to external PWM or internal ITRIP regulation.