SLVSGT3 December   2022 DRV8317

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Control Modes
        1. 8.3.2.1 6x PWM Mode
        2. 8.3.2.2 3x PWM Mode
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  AVDD Linear Voltage Regulator
      5. 8.3.5  Charge Pump
      6. 8.3.6  Slew Rate Control
      7. 8.3.7  Cross Conduction (Dead Time)
      8. 8.3.8  Propagation Delay
      9. 8.3.9  Pin Diagrams
        1. 8.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.9.3 Open Drain Pin
        4. 8.3.9.4 Push Pull Pin
        5. 8.3.9.5 Four Level Input Pin
      10. 8.3.10 Current Sense Amplifiers
        1. 8.3.10.1 Current Sense Amplifier Operation
      11. 8.3.11 Protections
        1. 8.3.11.1 Under Voltage Protection (UVP)
        2. 8.3.11.2 VM Under Voltage Warn (VMUV_WARN) Protection
          1. 8.3.11.2.1 VM Under Voltage Warn Automatic Retry (VMUV_WARN_MODE = 00b or 01b)
          2. 8.3.11.2.2 VM Under Voltage Warn Report Only (VMUV_WARN_MODE = 10b)
          3. 8.3.11.2.3 VM Under Voltage Warn Disabled (VMUV_WARN_MODE = 11b)
        3. 8.3.11.3 Over Current Protection (OCP)
          1. 8.3.11.3.1 OCP Latched Fault (OCP_MODE = 010b)
          2. 8.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)
          3. 8.3.11.3.3 OCP Report Only (OCP_MODE = 011b)
        4. 8.3.11.4 VM Over Voltage Protection (OVP)
        5. 8.3.11.5 SPI Fault
        6. 8.3.11.6 System (OTP Read) Fault
        7. 8.3.11.7 Thermal Protection
          1. 8.3.11.7.1 FET Over Temperature Warning (OTW_FET)
          2. 8.3.11.7.2 FET Over Temperature Shutdown (OTS_FET)
          3. 8.3.11.7.3 LDO Over Temperature Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (FLT_CLR or nSLEEP Reset Pulse)
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI Format
    6. 8.6 DRV8317 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
        2. 9.2.1.2 Driver Propagation Delay and Dead Time
        3. 9.2.1.3 Delay Compensation
        4. 9.2.1.4 Current Sensing and Output Filtering
        5. 9.2.1.5 Application Curves
    3. 9.3 Alternate Applications
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation and Junction Temperature Estimation
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6 DRV8317 Registers

Table 8-9 lists the memory-mapped registers for the DRV8317 registers. All register offset addresses not listed in Table 8-9 should be considered as reserved locations and the register contents should not be modified.

Table 8-9 DRV8317 Registers
OffsetAcronymRegister NameSection
0hDEV_STSDevice Status Register#DRV8317_DRV8317_DRV8317_DEV_STS
2hDEV_RSTSDevice Raw Status Register#DRV8317_DRV8317_DRV8317_DEV_RSTS
4hOT_STSOver Temperature Status Register#DRV8317_DRV8317_DRV8317_OT_STS
5hSUP_STSSupply Status Register#DRV8317_DRV8317_DRV8317_SUP_STS
6hDRV_STSDriver Status Register#DRV8317_DRV8317_DRV8317_DRV_STS
7hSYSIF_STSSystem Interface Status Register#DRV8317_DRV8317_DRV8317_SYSIF_STS
10hFLT_MODEFault Mode Register#DRV8317_DRV8317_DRV8317_FLT_MODE
12hSYSF_CTRLSystem Fault Control Register#DRV8317_DRV8317_DRV8317_SYSF_CTRL
13hDRVF_TCTRLDriver Fault Control Register#DRV8317_DRV8317_DRV8317_DRVF_TCTRL
16hFLT_TCTRLFault Timing Control Register#DRV8317_DRV8317_DRV8317_FLT_TCTRL
17hFLT_CLRFault Clear Register#DRV8317_DRV8317_DRV8317_FLT_CLR
18hVMUV_WARN_THRVM Under Voltage Warn Threshold Register#DRV8317_DRV8317_DRV8317_VMUV_WARN_THR
20hPWM_CTRLPWM Control Register#DRV8317_DRV8317_DRV8317_PWM_CTRL
22hDRV_CTRLPredriver control Register#DRV8317_DRV8317_DRV8317_DRV_CTRL
23hCSA_CTRLCSA Control Register#DRV8317_DRV8317_DRV8317_CSA_CTRL
3FhSYS_CTRLSystem Control Register#DRV8317_DRV8317_DRV8317_SYS_CTRL

Complex bit access types are encoded to fit into small table cells. Table 8-10 shows the codes that are used for access types in this section.

Table 8-10 DRV8317 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.6.1 DEV_STS Register (Offset = 0h) [Reset = 0280h]

DEV_STS is shown in Figure 8-28 and described in Table 8-11.

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Figure 8-28 DEV_STS Register
15141312111098
PARITYRESERVEDDNRDY_STSSYSFLT
R-0hR-0-0hR-0-1hR-0h
76543210
RESETSPIFLTOCPUVWOVPUVPOTFFAULT
R-1hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 8-11 DEV_STS Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-10RESERVEDR-00h Reserved
9DNRDY_STSR-01h Device not ready status
0h = Device is ready to spin motor
1h = Device is not ready
8SYSFLTR0h OTP read fault occurred. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No OTP read fault is detected
1h = OTP read fault detected
7RESETR1h Device power on status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = Cleared by writing 1b to FLT_CLR bit after power-up
1h = Device has undergone power on reset
6SPIFLTR0h SPI fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No SPI fault is detected
1h = SPI fault is detected
5OCPR0h Driver over current Status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No over current condition is detected
1h = Over current condition is detected
4UVWR0h VM under voltage warning fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No VM under voltage warn condition is detected
1h = VM under voltage warn condition is detected
3OVPR0h Over voltage status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No over voltage condition is detected
1h = Over voltage condition is detected
2UVPR0h Supply under voltage status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No under voltage condition is detected on VM or CP
1h = Under voltage condition is detected on VM or CP
1OTFR0h Over temperature fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No over temperature warning / shutdown is detected
1h = Over temperature warning / shutdown is detected
0FAULTR0h Device fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No fault condition is detected
1h = Fault condition is detected

8.6.2 DEV_RSTS Register (Offset = 2h) [Reset = 0000h]

DEV_RSTS is shown in Figure 8-29 and described in Table 8-12.

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Figure 8-29 DEV_RSTS Register
15141312111098
RESERVEDDNRDY_RSTSSYSF_RSTS
R-0-0hR-0hR-0h
76543210
RESERVEDSPIF_RSTSOCP_RSTSVMUV_WRSTSOVP_RSTSUVP_RSTSOTF_RSTSRESERVED
R-0-0hR-0hR-0hR-0-0hR-0-0hR-0hR-0hR-0-0h
Table 8-12 DEV_RSTS Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR-00h Reserved
9DNRDY_RSTSR0h Device not ready indicator
0h = Device not ready to drive PWMs
1h = Device ready to drive PWMs
8SYSF_RSTSR0h OTP parity error during load, raw status. Cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No parity error during OTP load
1h = Parity error occurred during OTP load
7RESERVEDR-00h Reserved
6SPIF_RSTSR0h SPI fault raw status. Cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No SPI fault is detected
1h = SPI fault is detected
5OCP_RSTSR0h Driver OCP raw status. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current condition is detected
1h = Over current condition is detected
4VMUV_WRSTSR-00h VM under voltage warning fault raw status. Auto cleared if retry is enabled in VMUV_WARN_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No VM under voltage warn condition is detected (VM > VMUV_WARN_RISE threshold)
1h = VM under voltage warn condition is detected (VM < VMUV_WARN_FALL threshold)
3OVP_RSTSR-00h Over voltage protection fault raw status. Auto cleared if retry is enabled in OVP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over voltage condition on VM is detected
1h = VM over voltage condition is detected
2UVP_RSTSR0h Under voltage protection fault raw status. Auto cleared if retry is enabled in UVP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No under voltage condition is detected on VM or CP
1h = Under voltage condition is detected on VM or CP
1OTF_RSTSR0h Over temperature fault raw status. Auto cleared if retry is enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over temperature warning/shutdown is detected
1h = Over temperature warning/shutdown is detected
0RESERVEDR-00h Reserved

8.6.3 OT_STS Register (Offset = 4h) [Reset = 0000h]

OT_STS is shown in Figure 8-30 and described in Table 8-13.

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Figure 8-30 OT_STS Register
15141312111098
PARITYRESERVED
R-0hR-0-0h
76543210
RESERVEDRESERVEDOTW_FETOTS_FET
R-0-0hR-0hR-0hR-0h
Table 8-13 OT_STS Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-3RESERVEDR-00h Reserved
2RESERVEDR0h Reserved
1OTW_FETR0h FET over temperature warning fault status. Auto cleared if retry is enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No FET over temperature warning is detected
1h = FET over temperature warning is detected
0OTS_FETR0h FET over temperature shutdown fault status. Auto cleared if retry is enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No FET over temperature shutdown is detected
1h = FET over temperature shutdown is detected

8.6.4 SUP_STS Register (Offset = 5h) [Reset = 0000h]

SUP_STS is shown in Figure 8-31 and described in Table 8-14.

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Figure 8-31 SUP_STS Register
15141312111098
PARITYRESERVED
R-0hR-0-0h
76543210
VMUV_WARNVM_OVRESERVEDCP_UVRESERVEDRESERVEDVM_UVRESERVED
R-0-0hR-0-0hR-0-0hR-0hR-0-0hR-0hR-0-0hR-0h
Table 8-14 SUP_STS Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-8RESERVEDR-00h Reserved
7VMUV_WARNR-00h VM under voltage warning fault status. This bit is not auto cleared even when retry is enabled in VMUV_WARN_MODE. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No VM under voltage warning is detected
1h = VM under voltage warning is detected
6VM_OVR-00h VM over voltage fault status. This bit is not auto cleared even when retry is enabled in OVP_MODE. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No VM over voltage is detected
1h = VM over voltage is detected
5RESERVEDR-00h Reserved
4CP_UVR0h Charge pump under voltage fault status. This bit is not auto cleared even when retry is enabled in UVP_MODE. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No charge pump under voltage is detected
1h = Charge pump under voltage is detected
3RESERVEDR-00h Reserved
2RESERVEDR0h Reserved
1VM_UVR-00h VM under voltage fault status. This bit is not auto cleared even when retry is enabled in UVP_MODE. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No VM under voltage is detected
1h = VM under voltage is detected
0RESERVEDR0h Reserved

8.6.5 DRV_STS Register (Offset = 6h) [Reset = 0000h]

DRV_STS is shown in Figure 8-32 and described in Table 8-15.

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Figure 8-32 DRV_STS Register
15141312111098
PARITYRESERVED
R-0hR-0-0h
76543210
RESERVEDOCPC_HSOCPB_HSOCPA_HSRESERVEDOCPC_LSOCPB_LSOCPA_LS
R-0-0hR-0hR-0hR-0hR-0-0hR-0hR-0hR-0h
Table 8-15 DRV_STS Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-7RESERVEDR-00h Reserved
6OCPC_HSR0h Over current status on high-side MOSFET of OUTC. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on high-side MOSFET of OUTC
1h = Over current detected on high-side MOSFET of OUTC
5OCPB_HSR0h Over current status on high-side MOSFET of OUTB. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on high-side MOSFET of OUTB
1h = Over current detected on high-side MOSFET of OUTB
4OCPA_HSR0h Over current status on high-side MOSFET of OUTA. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on high-side MOSFET of OUTA
1h = Over current detected on high-side MOSFET of OUTA
3RESERVEDR-00h Reserved
2OCPC_LSR0h Over current status on low-side MOSFET of OUTC. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on low-side MOSFET of OUTC
1h = Over current detected on low-side MOSFET of OUTC
1OCPB_LSR0h Over current status on low-side MOSFET of OUTB. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on low-side MOSFET of OUTB
1h = Over current detected on low-side MOSFET of OUTB
0OCPA_LSR0h Over current status on low-side MOSFET of OUTA. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on low-side MOSFET of OUTA
1h = Over current detected on low-side MOSFET of OUTA

8.6.6 SYSIF_STS Register (Offset = 7h) [Reset = 0000h]

SYSIF_STS is shown in Figure 8-33 and described in Table 8-16.

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Figure 8-33 SYSIF_STS Register
15141312111098
PARITYRESERVED
R-0hR-0-0h
76543210
RESERVEDOTPLD_ERRRESERVEDSPI_PARITYBUS_CNTFRM_ERR
R-0-0hR-0hR-0-0hR-0hR-0hR-0h
Table 8-16 SYSIF_STS Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-5RESERVEDR-00h Reserved
4OTPLD_ERRR0h OTP parity error during load
0h = No OTP read error is detected
1h = OTP read error is detected
3RESERVEDR-00h Reserved
2SPI_PARITYR0h SPI parity error
0h = No SPI Parity Error is detected
1h = SPI Parity Error is detected
1BUS_CNTR0h SPI bus contention error
0h = No SPI Bus Contention Error is detected
1h = SPI Bus Contention Error is detected
0FRM_ERRR0h SPI frame error
0h = No SPI Frame Error is detected
1h = SPI Frame Error is detected

8.6.7 FLT_MODE Register (Offset = 10h) [Reset = 0015h]

FLT_MODE is shown in Figure 8-34 and described in Table 8-17.

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Figure 8-34 FLT_MODE Register
15141312111098
PARITYRESERVEDVMUV_WARN_MODEOVP_MODERESERVED
R/W-0hR-0-0hR/W-0hR/W-0hR/W-0h
76543210
SPIFLT_MODEOCP_MODEUVP_MODEOTF_MODE
R/W-0hR/W-1hR/W-1hR/W-1h
Table 8-17 FLT_MODE Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR/W0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-13RESERVEDR-00h Reserved
12-11VMUV_WARN_MODER/W0h VM under voltage warning fault mode
0h = Report on nFAULT, latch into status register, pre-driver Hi-Z, auto recovery with slow retry time (in ms)
1h = Report on nFAULT, latch into status register, pre-driver Hi-Z, auto recovery with fast retry time (in ms)
2h = Report on nFAULT, latch into status register, no action on pre-driver
3h = Disabled
10-9OVP_MODER/W0h Over voltage protection fault mode
0h = Report on nFAULT, latch into status register, pre-driver Hi-Z, auto recovery with slow retry time (in ms)
1h = Report on nFAULT, latch into status register, pre-driver Hi-Z, auto recovery with fast retry time (in ms)
2h = Reserved
3h = Reserved
8RESERVEDR/W0h Reserved
7SPIFLT_MODER/W0h SPI fault mode
0h = Report on nFAULT, latch into status register, no action on pre-driver
1h = Disabled
6-4OCP_MODER/W1h Over current protection fault mode
0h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recovery with slow retry time (in ms)
1h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recovery with fast retry time (in ms)
2h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, no auto recovery, wait for CLR_FLT
3h = Report on nFAULT, Latch into status register, No action on pre-driver
4h = Reserved
5h = Reserved
6h = Reserved
7h = Reserved
3-2UVP_MODER/W1h Under voltage protection fault mode
0h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recovery with slow retry time (in ms)
1h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recovery with fast retry time (in ms)
2h = Reserved
3h = Reserved
1-0OTF_MODER/W1h Over temperature fault mode
0h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recover with Slow Retry time (in ms)
1h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recover with Fast Retry time (in ms)
2h = Reserved
3h = Reserved

8.6.8 SYSF_CTRL Register (Offset = 12h) [Reset = 0553h]

SYSF_CTRL is shown in Figure 8-35 and described in Table 8-18.

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Figure 8-35 SYSF_CTRL Register
15141312111098
PARITYRESERVEDDNRDY_ENOTW_FET_ENRESERVED
R/W-0hR-0-0hR/W-1hR/W-0hR/W-1h
76543210
VMUV_WARN_ENRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-1hR-0-0hR/W-1hR-0-0hR/W-1hR/W-1h
Table 8-18 SYSF_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR/W0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-11RESERVEDR-00h Reserved
10DNRDY_ENR/W1h Device not ready fault enable
0h = Device not ready fault is disabled
1h = Device not ready fault is enabled
9OTW_FET_ENR/W0h FET over temperature warning fault enable
0h = FET over temperature warning is disabled
1h = FET over temperature warning is enabled
8RESERVEDR/W1h Reserved
7VMUV_WARN_ENR/W0h VM under voltage warn fault enable
0h = VM under voltage warning fault is disabled
1h = VM under voltage warning fault is enabled
6RESERVEDR/W1h Reserved
5RESERVEDR-00h Reserved
4RESERVEDR/W1h Reserved
3-2RESERVEDR-00h Reserved
1RESERVEDR/W1h Reserved
0RESERVEDR/W1h Reserved

8.6.9 DRVF_TCTRL Register (Offset = 13h) [Reset = 0155h]

DRVF_TCTRL is shown in Figure 8-36 and described in Table 8-19.

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Figure 8-36 DRVF_TCTRL Register
15141312111098
PARITYRESERVEDRESERVED
R/W-0hR-0-0hR/W-1h
76543210
RESERVEDOCP_DEGOCP_TBLANKVMUV_WARN_TDG
R/W-1hR/W-1hR/W-1hR/W-1h
Table 8-19 DRVF_TCTRL Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR/W0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-10RESERVEDR-00h Reserved
9-8RESERVEDR/W1h Reserved
7-6RESERVEDR/W1h Reserved
5-4OCP_DEGR/W1h OCP deglitch time
0h = 0.3 µs
1h = 0.6 µs
2h = 0.9 µs
3h = 1.2 µs
3-2OCP_TBLANKR/W1h OCP blanking time
0h = 0.3 µs
1h = 0.7 µs
2h = 2 µs
3h = 1.2 µs
1-0VMUV_WARN_TDGR/W1h VM under voltage warning deglitch time
0h = 0.3 µs
1h = 0.6 µs
2h = 0.9 µs
3h = 2 µs

8.6.10 FLT_TCTRL Register (Offset = 16h) [Reset = 0003h]

FLT_TCTRL is shown in Figure 8-37 and described in Table 8-20.

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Figure 8-37 FLT_TCTRL Register
15141312111098
PARITYRESERVED
R/W-0hR-0-0h
76543210
RESERVEDSLOW_TRETRYFAST_TRETRY
R-0-0hR/W-0hR/W-3h
Table 8-20 FLT_TCTRL Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR/W0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-4RESERVEDR-00h Reserved
3-2SLOW_TRETRYR/W0h Retry time (typical) for slow recovery from fault condition
0h = 0.5s
1h = 1s
2h = 2s
3h = 5s
1-0FAST_TRETRYR/W3h Retry time (typical) for fast recovery from fault condition
0h = 0.5ms
1h = 1ms
2h = 2ms
3h = 5ms

8.6.11 FLT_CLR Register (Offset = 17h) [Reset = 0000h]

FLT_CLR is shown in Figure 8-38 and described in Table 8-21.

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Figure 8-38 FLT_CLR Register
15141312111098
RESERVEDRESERVED
R/W-0hR-0-0h
76543210
RESERVEDFLT_CLR
R-0-0hW-0h
Table 8-21 FLT_CLR Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14-1RESERVEDR-00h Reserved
0FLT_CLRW0h Clear latched faults
0h = No clear fault command is issued
1h = To clear the latched fault bits. This bit automatically resets after being written.

8.6.12 VMUV_WARN_THR Register (Offset = 18h) [Reset = 0000h]

VMUV_WARN_THR is shown in Figure 8-39 and described in Table 8-22.

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Figure 8-39 VMUV_WARN_THR Register
15141312111098
PARITYRESERVED
R/W-0hR-0-0h
76543210
VMUV_WARN_RTHVMUV_WARN_FTH
R/W-0hR/W-0h
Table 8-22 VMUV_WARN_THR Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR/W0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-8RESERVEDR-00h Reserved
7-4VMUV_WARN_RTHR/W0h VM under voltage warning rising threshold
0h = 5.62V
1h = 6.25V
2h = 6.87V
3h = 7.5V
4h = 8.12V
5h = 8.75V
6h = 9.37V
7h = 10.00V
8h = 10.62V
9h = 11.25V
Ah = 11.87V
Bh = 12.5V
Ch = 13.75V
Dh = 15.00V
Eh = 16.25V
Fh = 17.5V
3-0VMUV_WARN_FTHR/W0h VM under voltage warning falling threshold
0h = 5.4V
1h = 6.0V
2h = 6.6V
3h = 7.2V
4h = 7.8V
5h = 8.4V
6h = 9.0V
7h = 9.6V
8h = 10.2V
9h = 10.8V
Ah = 11.4V
Bh = 12.0V
Ch = 13.2V
Dh = 14.4V
Eh = 15.6V
Fh = 16.8V

8.6.13 PWM_CTRL Register (Offset = 20h) [Reset = 0000h]

PWM_CTRL is shown in Figure 8-40 and described in Table 8-23.

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Figure 8-40 PWM_CTRL Register
15141312111098
PARITYRESERVED
R/W-0hR-0-0h
76543210
RESERVEDSSC_DISPWM_MODE
R-0-0hR/W-0hR/W-0h
Table 8-23 PWM_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR/W0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-3RESERVEDR-00h Reserved
2SSC_DISR/W0h Disable SSC on oscillator
0h = SSC enabled
1h = SSC disabled
1-0PWM_MODER/W0h PWM mode selection
0h = 6x mode
1h = 6x direct mode
2h = 3x mode
3h = 3x direct mode

8.6.14 DRV_CTRL Register (Offset = 22h) [Reset = 0003h]

DRV_CTRL is shown in Figure 8-41 and described in Table 8-24.

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Figure 8-41 DRV_CTRL Register
15141312111098
PARITYRESERVEDDLY_TARGET
R/W-0hR-0-0hR/W-0h
76543210
DLYCMP_ENRESERVEDSLEW_RATE
R/W-0hR-0-0hR/W-3h
Table 8-24 DRV_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR/W0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12RESERVEDR-00h Reserved
11-8DLY_TARGETR/W0h Delay Target : DLY_TARGET * 0.2µs
7DLYCMP_ENR/W0h Driver Delay Compensation enable
0h = Delay compensation disabled
1h = Delay compensation enabled
6-2RESERVEDR-00h Reserved
1-0SLEW_RATER/W3h Slew rate settings
0h = Slew rate is 25 V/µs
1h = Slew rate is 50 V/µs
2h = Slew rate is 125 V/µs
3h = Slew rate is 200 V/µs

8.6.15 CSA_CTRL Register (Offset = 23h) [Reset = 0008h]

CSA_CTRL is shown in Figure 8-42 and described in Table 8-25.

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Figure 8-42 CSA_CTRL Register
15141312111098
PARITYRESERVED
R/W-0hR-0-0h
76543210
RESERVEDCSA_ENRESERVEDCSA_GAIN
R-0-0hR/W-1hR-0-0hR/W-0h
Table 8-25 CSA_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR/W0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-4RESERVEDR-00h Reserved
3CSA_ENR/W1h Enable CSA
0h = CSA is disabled
1h = CSA is enabled
2RESERVEDR-00h Reserved
1-0CSA_GAINR/W0h CSA Gain settings
0h = CSA gain is 0.25 V/A
1h = CSA gain is 0.5 V/A
2h = CSA gain is 1 V/A
3h = CSA gain is 2 V/A

8.6.16 SYS_CTRL Register (Offset = 3Fh) [Reset = 5008h]

SYS_CTRL is shown in Figure 8-43 and described in Table 8-26.

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Figure 8-43 SYS_CTRL Register
15141312111098
PARITYWRITE_KEYRESERVEDRESERVEDRESERVED
R/W-0hW-5hR-0-0hR/W-0hR/W-0h
76543210
REG_LOCKSPI_PENRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-1hR/W-0h
Table 8-26 SYS_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15PARITYR/W0h Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-12WRITE_KEYW5h 0x5 : Write Key specific to this register.
11-10RESERVEDR-00h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7REG_LOCKR/W0h Register Lock Bit
0h = Registers Unlocked
1h = Registers Locked
6SPI_PENR/W0h Parity Enable for SPI
0h = Parity Disabled
1h = Parity Enabled
5-4RESERVEDR/W0h Reserved
3RESERVEDR/W1h Reserved
2-0RESERVEDR/W0h Reserved