SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
If the FET temperature exceeds the over temperature warning (TOTW_FET) threshold, the FAULT, OTF bits (in DEV_STS register) and OTW_FET bit (in OT_STS register) are set to 1b and the nFAULT pin is driven low. The nFAULT pin is released and OTW_FET is set to 0b once retry time (tRETRY) elapses after the FET temperature falls below the over temperature warning (TOTW_FET - TOTW_FET_HYS) threshold. The FAULT, OTF bits stay set to 1b until cleared through the CLR_FLT bit or an nSLEEP reset pulse (tRST).
Retry time (tRETRY) is set by,
In DRV8317H, FET over temperature warning is disabled.