SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
DRV8317 has under voltage protection enabled for VM, VIN_AVDD, AVDD and CP voltage rails - these fault protections cannot be disabled. VM, VIN_AVDD and AVDD under voltage faults result in device reset; CP under voltage fault response is user configurable through UVP mode.
If at any time, the voltage on VIN_AVDD or AVDD pin falls below the corresponding under voltage falling threshold (VVINAVDD_UV or VAVDD_UV), DRV8317 enters reset - in reset, FETs are in Hi-Z, pre-driver, charge pump, current sense amplifier and digital logic are disabled. Normal device operation resumes automatically after the respective rail voltage rises above the corresponding under voltage rising threshold (VVINAVDD_UV or VAVDD_UV) as shown in Figure 8-22.
If at any time the voltage on VM or CP pin falls below the corresponding under voltage falling threshold (VVM_UV or VCP_UV), FETs are in Hi-Z, charge pump is disabled, nFAULT pin is driven low, FAULT and UVP in DEV_STS and VM_UV or CP_UV in SUP_STS are set to 1b. Normal operation resumes automatically (pre-driver, charge pump operation and the nFAULT pin is released) once the retry time (tRETRY) lapses after VM or CP voltage is above the corresponding under voltage rising threshold (VVM_UV or VCP_UV) as shown in Figure 8-23. The FAULT, UVP and UV_UV or CP_UV bits stay set to 1b until a clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST).
Retry time (tRETRY) is set by,
IN DRV8317H, UVP_MODE is set to 01b and FAST_TRETRY is fixed at 5-ms.