SLVSGT3 December   2022 DRV8317

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Control Modes
        1. 8.3.2.1 6x PWM Mode
        2. 8.3.2.2 3x PWM Mode
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  AVDD Linear Voltage Regulator
      5. 8.3.5  Charge Pump
      6. 8.3.6  Slew Rate Control
      7. 8.3.7  Cross Conduction (Dead Time)
      8. 8.3.8  Propagation Delay
      9. 8.3.9  Pin Diagrams
        1. 8.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.9.3 Open Drain Pin
        4. 8.3.9.4 Push Pull Pin
        5. 8.3.9.5 Four Level Input Pin
      10. 8.3.10 Current Sense Amplifiers
        1. 8.3.10.1 Current Sense Amplifier Operation
      11. 8.3.11 Protections
        1. 8.3.11.1 Under Voltage Protection (UVP)
        2. 8.3.11.2 VM Under Voltage Warn (VMUV_WARN) Protection
          1. 8.3.11.2.1 VM Under Voltage Warn Automatic Retry (VMUV_WARN_MODE = 00b or 01b)
          2. 8.3.11.2.2 VM Under Voltage Warn Report Only (VMUV_WARN_MODE = 10b)
          3. 8.3.11.2.3 VM Under Voltage Warn Disabled (VMUV_WARN_MODE = 11b)
        3. 8.3.11.3 Over Current Protection (OCP)
          1. 8.3.11.3.1 OCP Latched Fault (OCP_MODE = 010b)
          2. 8.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)
          3. 8.3.11.3.3 OCP Report Only (OCP_MODE = 011b)
        4. 8.3.11.4 VM Over Voltage Protection (OVP)
        5. 8.3.11.5 SPI Fault
        6. 8.3.11.6 System (OTP Read) Fault
        7. 8.3.11.7 Thermal Protection
          1. 8.3.11.7.1 FET Over Temperature Warning (OTW_FET)
          2. 8.3.11.7.2 FET Over Temperature Shutdown (OTS_FET)
          3. 8.3.11.7.3 LDO Over Temperature Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (FLT_CLR or nSLEEP Reset Pulse)
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI Format
    6. 8.6 DRV8317 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
        2. 9.2.1.2 Driver Propagation Delay and Dead Time
        3. 9.2.1.3 Delay Compensation
        4. 9.2.1.4 Current Sensing and Output Filtering
        5. 9.2.1.5 Application Curves
    3. 9.3 Alternate Applications
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation and Junction Temperature Estimation
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 DRV8317S 36-Pin WQFN With Exposed Thermal Pad Top View
Figure 6-2 DRV8317H 36-Pin WQFN With Exposed Thermal Pad Top View
Table 6-1 Pin Functions
PIN 36-pin package TYPE(1) DESCRIPTION
NAME DRV8317S DRV8317H
AGND 21 21 GND Device analog ground. Connect to a separate ground plane.2
AVDD 22 22 PWR O 3.3V regulator output. Connect a X5R or X7R, 2.2-µF (no load) or 4.7-µF (up to 80mA load), 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 80 mA for external loads.
CP 6 6 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP and VM pins.
CPH 5 5 PWR Charge pump switching node. Connect a X5R or X7R, 100-nF, (2xVM)- rated ceramic capacitor between the CPH and CPL pins.
CPL 4 4 PWR
CSAREF 33 33 PWR I Current sense amplifier power supply input/reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the CSAREF and AGND pins.
GAIN — 29 I Available only in hardware variant (DRV8317H). The pin is a 4-level input pin for current sense amplifier gain setting.
INHA 23 23 I High-side driver control input for OUTA. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode.
INHB 25 25 I High-side driver control input for OUTB. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode.
INHC 27 27 I High-side driver control input for OUTC. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode.
INLA 24 24 I Low-side driver control input for OUTA. This pin controls the state of the low-side MOSFET in 6x PWM Mode.
INLB 26 26 I Low-side driver control input for OUTB. This pin controls the state of the low-side MOSFET in 6x PWM Mode.
INLC 28 28 I Low-side driver control input for OUTC. This pin controls the state of the low-side MOSFET in 6x PWM Mode.
MODE — 31 I Available only in hardware variant (DRV8317H). This is a 4-level input pin for PWM mode setting.
NC 3 3, 32 — No connect. Leave the pin floating.
nFAULT 2 2 O Fault indication pin. Pulled low during fault condition. Open-drain output; requires an external pull-up resistor to AVDD.
nSCS 32 — I Available only in SPI variant (DRV8317S). Serial chip select. A logic low on this pin enables serial interface communication.
nSLEEP 1 1 I When this pin is logic low the device goes to a low-power sleep mode. A 15 to 50-µs low pulse on nSLEEP pin can be used to reset fault conditions without entering sleep mode.
OUTA 11, 12 11, 12 O Half-bridge output A. Connect to motor winding.
OUTB 14, 15 14, 15 O Half-bridge output B. Connect to motor winding.
OUTC 17, 18 17, 18 O Half-bridge output C. Connect to motor winding.
PGND 10, 13, 16, 19 10, 13, 16, 19 PWR Device power ground. Connect to a separate ground plane.2
SCLK 31 — I Available only in SPI variant (DRV8317S). Serial clock input. Serial data is shifted out on the rising edge and captured on the falling edge of SCLK.
SDI 30 — I Available only in SPI variant (DRV8317S). Serial data input. Data (input) is captured on the falling edge of the SCLK pin (SPI devices).
SDO 29 — O Available only in SPI variant (DRV8317S). Serial data output. Data (output) is shifted out on the rising edge of the SCLK pin.
SLEW — 30 I Available only in hardware variant (DRV8317H). This pin is a 4-level input pin for OUTx voltage slew rate setting.
SOA 36 36 O Current sense amplifier output for OUTA.
SOB 35 35 O Current sense amplifier output for OUTB.
SOC 34 34 O Current sense amplifier output for OUTC.
VIN_AVDD 7 7 PWR Input supply for AVDD LDO
VM 8, 9, 20 8, 9, 20 PWR Device and motor power supply. Connect to motor supply voltage; bypass to PGND with a 0.1-µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device
Thermal pad PWR Must be connected to AGND.
(1) I = input, O = output, PWR = power, GND = ground, NC = no connect