SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
If the FET temperature exceeds the shutdown threshold (TOTS_FET), all the integrated FETs are in Hi-Z, the FAULT, OTF bits (in DEV_STS register) and OTS_FET bit (in OT_STS register) are set to 1b and the nFAULT pin is driven low. Normal operation resumes automatically (pre-driver operation, nFAULT pin is released and OTS_FET is set to 0b) after retry time (tRETRY) elapses, if FET temperature falls below the over temperature shutdown (TOTS_FET - TOTS_FET_HYS) threshold. The FAULT, OTF bits stay set to 1b until cleared through the CLR_FLT bit or an nSLEEP reset pulse (tRST). This feature cannot be disabled.
Retry time (tRETRY) is set by,
IN DRV8317H, tRETRY period is fixed at 5-ms.