SLVSDY6A August   2018  – June  2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R


  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions—32-Pin DRV8350 Devices
    2.     Pin Functions—48-Pin DRV8350R Devices
    3.     Pin Functions—40-Pin DRV8353 Devices
    4.     Pin Functions—48-Pin DRV8353R Devices
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three Phase Smart Gate Drivers
        1. PWM Control Modes
          1. 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
          2. 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
          3. 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
          4. Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
        2. Device Interface Modes
          1. Serial Peripheral Interface (SPI)
          2. Hardware Interface
        3. Gate Driver Voltage Supplies and Input Supply Configurations
        4. Smart Gate Drive Architecture
          1. IDRIVE: MOSFET Slew-Rate Control
          2. TDRIVE: MOSFET Gate Drive Control
          3. Propagation Delay
          4. MOSFET VDS Monitors
          5. VDRAIN Sense and Reference Pin
      2. 8.3.2 DVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)
        1. Bidirectional Current Sense Operation
        2. Unidirectional Current Sense Operation (SPI only)
        3. Amplifier Calibration Modes
        4. MOSFET VDS Sense Mode (SPI Only)
      5. 8.3.5 Step-Down Buck Regulator
        1. Functional Block Diagram
        2. Feature Description
          1. Control Circuit Overview
          2. Start-Up Regulator (VCC)
          3. Regulation Comparator
          4. Overvoltage Comparator
          5. On-Time Generator and Shutdown
          6. Current Limit
          7. N-Channel Buck Switch and Driver
          8. Thermal Protection
      6. 8.3.6 Gate Driver Protective Circuits
        1. VM Supply and VDRAIN Undervoltage Lockout (UVLO)
        2. VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
        3. MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. VDS Latched Shutdown (OCP_MODE = 00b)
          2. VDS Automatic Retry (OCP_MODE = 01b)
          3. VDS Report Only (OCP_MODE = 10b)
          4. VDS Disabled (OCP_MODE = 11b)
        4. VSENSE Overcurrent Protection (SEN_OCP)
          1. VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. VSENSE Automatic Retry (OCP_MODE = 01b)
          3. VSENSE Report Only (OCP_MODE = 10b)
          4. VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
        5. Gate Driver Fault (GDF)
        6. Overcurrent Soft Shutdown (OCP Soft)
        7. Thermal Warning (OTW)
        8. Thermal Shutdown (OTSD)
        9. Fault Response Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. Sleep Mode
        2. Operating Mode
        3. Fault Reset (CLR_FLT or ENABLE Reset Pulse)
      2. 8.4.2 Buck Regulator Functional Modes
        1. Shutdown Mode
        2. Active Mode
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. SPI
          1. SPI Format
    6. 8.6 Register Maps
      1. 8.6.1 Status Registers
        1. Fault Status Register 1 (address = 0x00h)
          1. Table 11. Fault Status Register 1 Field Descriptions
        2. Fault Status Register 2 (address = 0x01h)
          1. Table 12. Fault Status Register 2 Field Descriptions
      2. 8.6.2 Control Registers
        1. Driver Control Register (address = 0x02h)
          1. Table 14. Driver Control Field Descriptions
        2. Gate Drive HS Register (address = 0x03h)
          1. Table 15. Gate Drive HS Field Descriptions
        3. Gate Drive LS Register (address = 0x04h)
          1. Table 16. Gate Drive LS Register Field Descriptions
        4. OCP Control Register (address = 0x05h)
          1. Table 17. OCP Control Field Descriptions
        5. CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
          1. Table 18. CSA Control Field Descriptions
        6. Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
          1. Table 19. Driver Configuration Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Primary Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. External MOSFET Support
            1. MOSFET Example
          2. IDRIVE Configuration
            1. IDRIVE Example
          3. VDS Overcurrent Monitor Configuration
            1. VDS Overcurrent Example
          4. Sense-Amplifier Bidirectional Configuration (DRV8353 and DRV8353R)
            1. Sense-Amplifier Example
          5. Single Supply Power Dissipation
          6. Single Supply Power Dissipation Example
          7. Buck Regulator Configuration (DRV8350R and DRV8353R)
        3. Application Curves
      2. 9.2.2 Alternative Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. Sense Amplifier Unidirectional Configuration
            1. Sense-Amplifier Example
            2. Dual Supply Power Dissipation
            3. Dual Supply Power Dissipation Example
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Buck-Regulator Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Bypass the VM pin to the GND pin using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 µF. Place this capacitor as near to the VM pin as possible with a thick trace or ground plane connected to the GND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be electrolytic. This capacitance must be at least 10 µF.

Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk capacitance should be placed such that it minimizes the length of any high current paths through the external MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.

Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for VDRAIN, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VDRAIN pins and VGLS and GNDs. These capacitors should be 1 µF, rated for 16 V, and be of type X5R or X7R.

Bypass the DVDD pin to the GND/DGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R or X7R. Place this capacitor as near to the pin as possible and minimize the path from the capacitor to the GND/DGND pin.

The VDRAIN pin can be shorted directly to the VM pin for single supply application configurations. However, if a significant distance is between the device and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side external MOSFETs. Do not connect the SLx pins directly to GND. Instead, use dedicated traces to connect these pins to the sources of the low-side external MOSFETs. These recommendations allow for more accurate VDS sensing of the external MOSFETs for overcurrent detection.

Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the low-side MOSFET source back to the SPx/SLx pins.