SLOSE59C May   2020  – July 2022 DRV8424 , DRV8425

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
    1.     Device Comparison Table
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  Current Regulation
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 Mixed Decay for Increasing and Decreasing Current
        4. 7.3.6.4 Smart tune Dynamic Decay
        5. 7.3.6.5 Smart tune Ripple Control
        6. 7.3.6.6 PWM OFF Time
        7. 7.3.6.7 Blanking time
      7. 7.3.7  Charge Pump
      8. 7.3.8  Linear Voltage Regulators
      9. 7.3.9  Logic Level, tri-level and quad-level Pin Diagrams
      10. 7.3.10 nFAULT Pin
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.11.3 Overcurrent Protection (OCP)
          1. 7.3.11.3.1 Latched Shutdown
          2. 7.3.11.3.2 Automatic Retry
        4. 7.3.11.4 Thermal Shutdown (OTSD)
          1. 7.3.11.4.1 Latched Shutdown
          2. 7.3.11.4.2 Automatic Retry
        5. 7.3.11.5 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)
      3. 7.4.3 Operating Mode (nSLEEP = 1, ENABLE = Hi-Z/1)
      4. 7.4.4 nSLEEP Reset Pulse
      5. 7.4.5 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
      4. 8.2.4 Thermal Application
        1. 8.2.4.1 Power Dissipation
          1. 8.2.4.1.1 Conduction Loss
          2. 8.2.4.1.2 Switching Loss
          3. 8.2.4.1.3 Power Dissipation Due to Quiescent Current
          4. 8.2.4.1.4 Total Power Dissipation
        2. 8.2.4.2 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.4.1.1 Conduction Loss

The current path for a motor connected in full-bridge is through the high-side FET of one half-bridge and low-side FET of the other half-bridge. The conduction loss (PCOND) depends on the motor rms current (IRMS) and high-side (RDS(ONH)) and low-side (RDS(ONL)) on-state resistances as shown in Equation 2.

Equation 2. PCOND = 2 x (IRMS)2 x (RDS(ONH) + RDS(ONL))

The conduction loss for the typical application shown in Table 8-2 is calculated in Equation 3.

Equation 3. PCOND = 2 x (IRMS)2 x (RDS(ONH) + RDS(ONL)) = 2 x (2-A / √2)2 x (0.165-Ω + 0.165-Ω) = 1.32-W
Note:

This power calculation is highly dependent on the device temperature which significantly effects the high-side and low-side on-resistance of the FETs. For more accurate calculation, consider the dependency of on-resistance of FETs with device temperature.