SNLS514C November   2015  – October 2019 DS280BR810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics -- Serial Management Bus Interface
    7. 6.7 Timing Requirements -- Serial Management Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 AC-Coupled Receiver and Transmitter
      3. 7.3.3 Signal Detect
      4. 7.3.4 2-Stage CTLE
      5. 7.3.5 Driver DC Gain Control
      6. 7.3.6 FIR Filter (Limiting Mode)
      7. 7.3.7 Configurable SMBus Address
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Slave Mode Configuration
      2. 7.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 7.5 Programming
      1. 7.5.1 Transfer of Data with the SMBus Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Types: Global, Shared, and Channel
      2. 7.6.2 Global Registers: Channel Selection and ID Information
        1. Table 2. Global Register Map
      3. 7.6.3 Shared Registers
        1. Table 3. Shared Register Map
      4. 7.6.4 Channel Registers
        1. Table 4. Channel Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Backplane and Mid-Plane Reach Extension
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Front-Port Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documents
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.4 Channel Registers

Table 4. Channel Register Map

Addr [HEX] Bit Default [HEX] Mode EEPROM Field Description
0x00 0x00 General
7 0 RW N CLK_CORE_DISAB 1: Disables 10 M core clock. This is the main clock domain for all the state machines.
0: Normal operation
6 0 RW N CLK_REGS_EN 1: Force enable the clock to the registers. Normally, the register clock is enabled automatically on a needed basis.
0: Normal operation
5 0 RW N RESERVED RESERVED
4 0 RW N CLK_REF_DISAB 1: Disables the 25 MHz CAL_CLK domain.
0: Normal operation
3 0 RW N RST_CORE 1: Reset the 10 M core clock domain. This is the main clock domain for all the state machines.
0: Normal operation
2 0 RWSC N RST_REGS 1: Reset channel registers to power-up defaults.
0: Normal operation
1 0 RW N RESERVED RESERVED
0 0 RW N RST_CAL_CLK 1: Resets the 25 MHz reference clock domain.
0: Normal operation
0x01 0x00 SIG_DET
7 0 R N SIGDET Signal detect status.
1: Signal detected at RX inputs.
0: No signal detected at RX inputs.
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 R N RESERVED RESERVED
2 0 R N RESERVED RESERVED
1 0 R N RESERVED RESERVED
0 0 R N RESERVED RESERVED
0x02 0x00
7 0 R N RESERVED RESERVED
6 0 R N RESERVED RESERVED
5 0 R N RESERVED RESERVED
4 0 R N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x03 0x80 CTLE_BOOST
7 1 RW Y EQ_BW[1] EQ stage one buffer current (strength) control. Impacts EQ bandwidth. 2'b11 yields highest bandwidth, 2'b00 yields lowest bandwidth. Refer to the Programming Guide for more information.
6 0 RW Y EQ_BW[0]
5 0 RW Y EQ_BST2[2] EQ boost stage 2 controls. Directly goes to analog. No override bit is needed. Refer to the Programming Guide for more information.
4 0 RW Y EQ_BST2[1]
3 0 RW Y EQ_BST2[0]
2 0 RW Y EQ_BST1[2] EQ boost stage 1 controls. Directly goes to analog. No override bit is needed. Refer to the Programming Guide for more information.
1 0 RW Y EQ_BST1[1]
0 0 RW Y EQ_BST1[0]
0x04 0x90
7 1 RW N RESERVED RESERVED
6 0 RW N EQ_PD_SD 1: Power down signal detect
0: Normal operation
5 0 RW Y EQ_HIGH_GAIN 1: Enable EQ high gain
0: Enable EQ low gain
4 1 RW Y EQ_EN_DC_OFF RESERVED
3 0 RW Y EQ_PD_EQ 1: Power down EQ
0: Enable EQ
2 0 RW N RESERVED RESERVED
1 0 RW Y BG_SEL_IPP100[2] CTLE bias programming. BG_SEL_IPP100[1:0] is in Reg_0x0F[5:4].
0 0 RW Y EQ_EN_BYPASS 1: Enable EQ bypass
0: Normal operation, signal travels through EQ.
0x05 0x04 SIG_DET_CONFIG
7 0 RW Y EQ_SD_PRESET 1: Force signal detect result to 1
0: Normal operation
This bit should not be set if 0x05[6] is also set.
6 0 RW Y EQ_SD_RESET 1: Force signal detect result to 0
0: Normal operation
This bit should not be set if 0x05[7] is also set.
5 0 RW Y EQ_REFA_SEL[1] Signal detect assert thresholds. Refer to the Programming Guide for more information.
4 0 RW Y EQ_REFA_SEL[0]
3 0 RW Y EQ_REFD_SEL[1] Signal detect de-assert thresholds. Refer to the Programming Guide for more information.
2 1 RW Y EQ_REFD_SEL[0]
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x06 0xC0 GPIO2 Config
7 1 RW Y DRV_SEL_VOD[1] Driver VOD adjust (DC gain), applicable to both linear and FIR limiting mode. Refer to the Programming Guide for more information.
6 1 RW Y DRV_SEL_VOD[0]
5 0 RW Y DRV_EQ_PD_OV 1: Driver and equalizer power down manually with Reg_0x06[3] and Reg_0x04[3], respectively.
0: Driver and equalizer are powered down/up by default when LOS=1/0.
4 0 RW Y DRV_SEL_MUTE
_OV		 Driver mute override:
1: Use register 0x06[1] for mute control.
0: Normal operation. Mute is automatically controlled by signal detect.
3 0 RW Y DRV_PD 1: Power down the driver.
0: Normal operation, driver power on or off is controlled by signal detect.
2 0 RW Y DRV_PD_CM_LOOP 1: Disable the driver’s common mode loop control circuit.
0: Normal operation, common mode loop enabled.
1 0 RW Y DRV_SEL_MUTE 1: Mute driver if override bit is enabled.
0: Normal operation
0 0 RW Y DRV_SEL_FIR Linear versus Limiting Mode select. Refer to the Programming Guide for more information.
1: Enable Limiting FIR mode.
0: Enable Linear mode (disable limiting FIR).
0x07 0x20
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 1 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x08 0x54
7 0 RW Y RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 0 RW Y RESERVED RESERVED
4 1 RW Y RESERVED RESERVED
3 0 RW Y BG_SEL_IPTAT25 1: Increases the current to the CTLE by 5%.
0: Default
2 1 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x09 0x00
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x0A 0x30
7 0 RW N RESERVED RESERVED
6 0 RW Y RESERVED RESERVED
5 1 RW Y SD_REF_HIGH Signal detect threshold controls:
11: Normal operation
10: Signal detect assert or de-assert thresholds reduced.
01: Signal detect assert or de-assert thresholds reduced.
00: Signal detect assert or de-assert thresholds reduced.
4 1 RW Y SD_GAIN
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x0B 0x1A
7 0 RW N RESERVED RESERVED
6 0 RW Y RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 1 RW Y FIR_MAIN[4] FIR Limiting mode main-cursor control. Refer to the Programming Guide for more information.
3 1 RW Y FIR_MAIN[3]
2 0 RW Y FIR_MAIN[2]
1 1 RW Y FIR_MAIN[1]
0 0 RW Y FIR_MAIN[0]
0x0C 0x40
7 0 RW N RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW Y FIR_PST[3] FIR Limiting mode post-cursor control. There is no sign bit for the post-cursor. The post-cursor always provides a high-pass filter effect. Refer to the Programming Guide for more information.
2 0 RW Y FIR_PST[2]
1 0 RW Y FIR_PST[1]
0 0 RW Y FIR_PST[0]
0x0D 0x40
7 0 RW N RESERVED RESERVED
6 1 RW Y RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW Y FIR_PRE[3] FIR Limiting mode pre-cursor control. There is no sign bit for the pre-cursor. The pre-cursor always provides a high-pass filter effect. Refer to the Programming Guide for more information.
2 0 RW Y FIR_PRE[2]
1 0 RW Y FIR_PRE[1]
0 0 RW Y FIR_PRE[0]
0x0E 0x00
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW N RESERVED RESERVED
4 0 RW N RESERVED RESERVED
3 0 RW N RESERVED RESERVED
2 0 RW N RESERVED RESERVED
1 0 RW N RESERVED RESERVED
0 0 RW N RESERVED RESERVED
0x0F 0x00
7 0 RW N RESERVED RESERVED
6 0 RW N RESERVED RESERVED
5 0 RW Y BG_SEL_IPP100[1] CTLE bias programming. BG_SEL_IPP100[2] is in Reg_0x04[1].
000: 0% additional current (Default)
001: 5% additional current
010: 10% additional current
011: 15% additional current
100: 20% additional current
101: 25% additional current
110: 30% additional current
111: 35% additional current
4 0 RW Y BG_SEL_IPP100[0]
3 0 RW Y BG_SEL_IPH200
_v1[1]		 Program pre-driver bias current:
00: 0% additional current (Default)
01: 12.5% additional current
10: 25% additional current
11: 37.5% additional current
2 0 RW Y BG_SEL_IPH200
_v1[0]
1 0 RW Y BG_SEL_IPH200
_v0[1]		 Program driver bias current:
00: 0% additional current (Default)
01: 12.5% additional current
10: 25% additional current
11: 37.5% additional current
0 0 RW Y BG_SEL_IPH200
_v0[0]