SNLS542C October   2016  – December 2020 DS280MB810

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements – Serial Management Bus Interface
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Data Path Operation
      2. 8.3.2 AC-coupled Receiver Inputs
      3. 8.3.3 Signal Detect
      4. 8.3.4 2-Stage CTLE
      5. 8.3.5 Driver DC Gain Control
      6. 8.3.6 2x2 Cross-point Switch
      7. 8.3.7 Configurable SMBus Address
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Slave Mode Configuration
      2. 8.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 8.5 Programming
      1. 8.5.1 Transfer of Data with the SMBus Interface
    6. 8.6 Register Maps
      1. 8.6.1 Register Types: Global, Shared, and Channel
      2. 8.6.2 Global Registers: Channel Selection and ID Information
      3. 8.6.3 Shared Registers
      4. 8.6.4 Channel Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Reach Extension
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Front-Port Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Pattern Generator Characteristics
        2. 9.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 9.2.3.3 Equalizing High Pre-Channel Loss
        4. 9.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Stripline Example
      2. 11.2.2 Microstrip Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 2x2 Cross-point Switch

Between each group of two adjacent channels (i.e. between channels 0–1, 2–3, 4–5, and 6–7) is a full 2x2 cross-point switch. The cross-point can be configured through pin-mode (shared register 0x05[1]=1) or SMBus registers (shared register 0x05[1]=0) to operate as follows:.

  • Straight-thru mode
  • Multiplex two inputs to one output
  • Fanout one input to two outputs
  • Cross two inputs to two outputs

Figure 8-1 shows the four 2x2 cross-points available in the DS280MB810, and Figure 8-2 shows how each cross-point can be configured for straight-thru, multiplex, de-multiplex, or cross-over applications. Refer to the DS280MB810 Programming Guide for details on how to program the cross-point through SMBus registers.

GUID-871BAC49-1DC1-4214-9E48-C904D149AF55-low.gifFigure 8-1 Block diagram showing all four 2x2 cross-points in the DS280MB810
GUID-0498685E-E006-4DD3-9AC5-F0C899E2AB67-low.gifFigure 8-2 Signal distribution options available in each 2x2 cross-point (channel A can be 0, 2, 4, or 6; channel B can be 1, 3, 5, or 7)

The switching operation of the cross-point can be configured with the MUXSEL0 and MUXSEL1 pins when shared register 0x05[1]=1. Note that shared register 0x05[1] of both quads must be set to 1 to enable pin-control cross-point mode. Each quad can be selected through Reg_0xFF[5:4]. Refer to the DS280MB810 Programming Guide for more information.

The behavior of the cross-point (i.e. straight-thru, fanout, or mux) for each state of MUXSEL is illustrated in Figure 8-3. Note that MUXSEL0 controls channels 0, 1, 4, and 5; and MUXSEL1 controls channels 2, 3, 6, and 7.

GUID-2060EB7F-AEB2-40E3-991C-0A92B9E27F50-low.gifFigure 8-3 Signal distribution configuration options when using pin-control mode (channel A can be 0, 2, 4, or 6; channel B can be 1, 3, 5, or 7)