SNLS543 August 2018 DS90UH949A-Q1
The D_GPIO[3:0] pins can be configured to obtain different sampling rates depending on the mode as well as back channel frequency. These different modes are controlled by a compatible deserializer. Consult the appropriate deserializer datasheet for details on how to configure the back channel frequency. See Table 2 for details about D_GPIOs in various modes.
|HSCC_MODE (ON DES)||MODE||NUMBER OF D_GPIOs||SAMPLES PER FRAME||D_GPIO EFFECTIVE FREQUENCY(1) (kHz)||D_GPIOs ALLOWED|
|5-Mbps BC(2)||10-Mbps BC(3)||20-Mbps BC(4)|