SNLS543 August   2018 DS90UH949A-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Applications Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Definition Multimedia Interface (HDMI)
        1. HDMI Receive Controller
      2. 7.3.2  Transition Minimized Differential Signaling
      3. 7.3.3  Enhanced Display Data Channel
      4. 7.3.4  Extended Display Identification Data (EDID)
        1. External Local EDID (EEPROM)
        2. Internal EDID (SRAM)
        3. External Remote EDID
        4. Internal Pre-Programmed EDID
      5. 7.3.5  Consumer Electronics Control (CEC)
      6. 7.3.6  +5-V Power Signal
      7. 7.3.7  Hot Plug Detect (HPD)
      8. 7.3.8  High-Speed Forward Channel Data Transfer
      9. 7.3.9  Back Channel Data Transfer
      10. 7.3.10 FPD-Link III Port Register Access
      11. 7.3.11 Power Down (PDB)
      12. 7.3.12 Serial Link Fault Detect
      13. 7.3.13 Interrupt Pin (INTB)
      14. 7.3.14 Remote Interrupt Pin (REM_INTB)
      15. 7.3.15 General-Purpose I/O
        1. GPIO[3:0] and D_GPIO[3:0] Configuration
        2. Back Channel Configuration
        3. GPIO_REG[8:5] Configuration
      16. 7.3.16 SPI Communication
        1. SPI Mode Configuration
        2. Forward Channel SPI Operation
        3. Reverse Channel SPI Operation
      17. 7.3.17 Backward Compatibility
      18. 7.3.18 Audio Modes
        1. HDMI Audio
        2. DVI I2S Audio Interface
          1. I2S Transport Modes
          2. I2S Repeater
        3. AUX Audio Channel
        4. TDM Audio Interface
      19. 7.3.19 HDCP
        1. HDCP I2S Audio Encryption
      20. 7.3.20 Built-In Self Test (BIST)
        1. BIST Configuration and Status
        2. Forward Channel and Back Channel Error Checking
      21. 7.3.21 Internal Pattern Generation
        1. Pattern Options
        2. Color Modes
        3. Video Timing Modes
        4. External Timing
        5. Pattern Inversion
        6. Auto Scrolling
        7. Additional Features
      22. 7.3.22 Spread Spectrum Clock Tolerance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Select Configuration Settings (MODE_SEL[1:0])
      2. 7.4.2 FPD-Link III Modes of Operation
        1. Single Link Operation
        2. Dual Link Operation
        3. Replicate Mode
        4. Auto-Detection of FPD-Link III Modes
        5. Frequency detection circuit may reset the FPD-Link III PLL during a temperature ramp
    5. 7.5 Programming
      1. 7.5.1 Serial Control Bus
      2. 7.5.2 Multi-Master Arbitration Support
      3. 7.5.3 I2C Restrictions on Multi-Master Operation
      4. 7.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 7.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 7.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
      7. 7.5.7 Prevention of I2C Faults During Abrupt System Faults
    6. 7.6 Register Maps
  8. Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. High-Speed Interconnect Guidelines
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

BIST Configuration and Status

The BIST mode is enabled at the deserializer by either the BISTEN pin or the BIST configuration register. The test may select either an external TMDS clock or the internal Oscillator clock (OSC) frequency. In the absence of the TMDS clock, the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration register.

When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received that contained one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel frame.

The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS output until a reset (through either a new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. LOCK is valid throughout the entire duration of BIST.

See Figure 18 for the BIST mode flow diagram.

Step 1: The Serializer is paired with another FPD-Link III Deserializer and BIST Mode is enabled through the BISTEN pin or through the register on the Deserializer. Right after BIST is enabled, part of the BIST sequence requires that bit 0x04[5] is toggled locally on the Serializer (set 0x04[5]=1, then set 0x04[5]=0). The desired clock source is selected either through the deserializer BISTC pin or through register on the Deserializer.

Step 2: An all-zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test result is held on the PASS pin. If the test ran error-free, the PASS output will remain HIGH. If one or more errors were detected, the PASS output will output constant LOW. The PASS output state is held until a new BIST is run, the device is RESET, or the device is powered down. The BIST duration is user-controlled by the duration of the BISTEN signal.

Step 4: The link returns to normal operation after the deserializer BISTEN pin is low. Figure 19 shows the waveform diagram of a typical BIST test for two cases: Case 1 is error-free, and Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data transmission and so forth), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing signal condition enhancements (Rx Equalization).

For more information on using BIST, refer to white paper: Using BIST on 94x.

DS90UH949A-Q1 BIST-mode-flow-diagram-SNLS543.gifFigure 18. BIST Mode Flow Diagram