SLLSES1E December   2015  – July 2025 HD3SS3220 , HD3SS3220L

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Cables, Adapters, and Direct Connect Devices
        1. 6.1.1.1 USB Type-C receptacles and Plugs
        2. 6.1.1.2 USB Type-C Cables
        3. 6.1.1.3 Legacy Cables and Adapters
        4. 6.1.1.4 Direct Connect Device
        5. 6.1.1.5 Audio Adapters
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  DFP/Source – Downstream Facing Port
      2. 6.3.2  UFP/Sink – Upstream Facing Port
      3. 6.3.3  DRP – Dual Role Port
      4. 6.3.4  Cable Orientation and Mux Control
      5. 6.3.5  Type-C Current Mode
      6. 6.3.6  Accessory Support
      7. 6.3.7  Audio Accessory
      8. 6.3.8  Debug Accessory
      9. 6.3.9  VCONN support for Active Cables
      10. 6.3.10 I2C and GPIO Control
      11. 6.3.11 HD3SS3220 V(BUS) Detection
      12. 6.3.12 VDD5 and VCC33 Power-On Requirements
    4. 6.4 Device Functional Modes
      1. 6.4.1 Unattached Mode
      2. 6.4.2 Active Mode
      3. 6.4.3 Dead Battery
      4. 6.4.4 Shutdown Mode
    5. 6.5 Programming
    6. 6.6 Register Maps
      1. 6.6.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
      2. 6.6.2 Connection Status Register (offset = 0x08) [reset = 0x00]
      3. 6.6.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]
      4. 6.6.4 General Control Register (offset = 0x0A) [reset = 0x00]
      5. 6.6.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application, DRP Port
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Typical Application, DFP Port
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
      4. 7.2.4 Typical Application, UFP Port
        1. 7.2.4.1 Design Requirements
        2. 7.2.4.2 Detailed Design Procedure
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Suggested PCB Stackups
      2. 9.1.2 High-Speed Signal Trace Length Matching
      3. 9.1.3 Differential Signal Spacing
      4. 9.1.4 High-Speed Differential Signal Rules
      5. 9.1.5 Symmetry in the Differential Pairs
      6. 9.1.6 Via Discontinuity Mitigation
      7. 9.1.7 Surface-Mount Device Pad Discontinuity Mitigation
      8. 9.1.8 ESD/EMI Considerations
    2. 9.2 Layout
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.12 VDD5 and VCC33 Power-On Requirements

The HD3SS3220 has two power supplies: VDD5 and VCC33. The VDD5 supply powers the internal CC controller and also provides VCONN to either CC1 or CC2. The VCC33 powers the 2:1 MUX.

The HD3SS3220 non-failsafe pins are the following: PORT, ADDR, SDA/OUT1, SCL/OUT2, INT_IN/OUT3, VCONN_FAULT_N, and DIR. If any of these non-failsafe pins are pulled-up to a supply other than VDD5, then VDD5 supply must be powered up before the VCC33 supply as depicted in Figure 6-2. If it is not possible to power up VDD5 before VCC33, then the ENn_CC pin must be held high while both supplies are ramping and then asserted low after both supplies are stable as depicted in Figure 6-3.

HD3SS3220 HD3SS3220L PowerOn Timings with ENn_CC always low Figure 6-2 PowerOn Timings with ENn_CC always low
HD3SS3220 HD3SS3220L PowerOn Timings with ENn_CC Controlled Figure 6-3 PowerOn Timings with ENn_CC Controlled