SLLSES1 Data sheet

SLLSES1E December 2015 – July 2025 HD3SS3220 , HD3SS3220L

PRODUCTION DATA

5.6 Timing Requirements

		MIN	MAX	UNIT
I2C (SDA, SCL)
t_SU:DAT	Data setup time	100		ns
t_HD:DAT	Data setup time	10		ns
t_SU;STA	Set-up time, SCL to start condition	0.6		µs
t_HD,STA	Hold time,(repeated) start condition to SCL	0.6		µs
t_SU:STO	Set up time for STOP condition	0.6		µs
t_VD;DAT	Data valid time		0.9	µs
t_VD;ACK	Data valid acknowledge time		0.9	µs
t_BUF	Bus free time between a STOP and START condition	1.3		µs
f_SCL	SCL clock frequency; I²C mode for local I²C control		400	ns
t_r	Rise time of both SDA and SCL signals		300	ns
t_f	Fall time of both SDA and SCL signals		300	ns
C_{BUS_100KHZ}	Total capacitive load for each bus line when operating at ≤ 100KHz		400	pF
C_{BUS_400KHZ}	Total capacitive load for each bus line when operating at 400KHz.		100	pF
SS MUX
t_PD	Switch propagation delay See Figure 5-3		80	ps
t_{SW_ON}	Switching time DIR-to-Switch ON See Figure 5-2		0.5	µs
t_{SW_OFF}	Switching time DIR-to-Switch OFF See Figure 5-2		0.5	µs
t_{SK_INTRA}	Intra-pair output skew See Figure 5-3		5	ps
t_{SK_INTER}	Inter-pair output skew See Figure 5-3		20	ps
Power-On Timings
t_{ENnCC_HI}	ENn_CC high after both VDD5 and VCC33 supplies are stable. Refer to Figure 6-3.	2		ms
t_{VDD5V_PG}	VDD5 stable before VCC33. Refer to Figure 6-2.	2		ms

Figure 5-1 Test Setup

Figure 5-2 Switch On and Off Timing Diagram

Figure 5-3 Timing Diagrams and Test Setup