SBOS062D September   2000  – December 2025 INA126 , INA2126

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: INA126
    5. 5.5 Thermal Information: INA2126
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Single-Supply Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting the Gain
        2. 7.2.2.2 Offset Trimming
        3. 7.2.2.3 Input Bias Current Return
        4. 7.2.2.4 Input Common-Mode Range
        5. 7.2.2.5 Input Protection
        6. 7.2.2.6 Channel Crosstalk—Dual Version
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Low-Voltage Operation
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

at TA = 25°C, VS = ±15V, RL = 25kΩ, VREF = 0V, and VCM = VS / 2, all chips site origins (CSO), unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset voltage (RTI) INA126P/U/E
INA2126P/U/E		 ±100 ±250 µV
INA126PA/UA/EA
INA2126PA/UA/EA		 ±150 ±500
Offset voltage drift (RTI) TA = –40°C to +85°C INA126P/U/E
INA2126P/U/E		 ±0.5 ±3 µV/°C
INA126PA/UA/EA
INA2126PA/UA/EA		 ±0.5 ±5
PSRR Power-supply rejection ratio (RTI) VS = ±1.35V to ±18V INA126P/U/E
INA2126P/U/E		 ±5 ±15 uV/V
INA126PA/UA/EA
INA2126PA/UA/EA		 ±5 ±50
Input impedance CSO: SHE 1 || 4 GΩ || pF
CSO: TID 17.5 || 1
Safe input voltage RS = 0Ω (V–) – 0.5 (V+) + 0.5 V
RS = 1kΩ (V–) – 10 (V+) + 10
VCM Common-mode voltage(1) –11.25 ±11.5 11.25 V
Channel seperation (dual) G = 5, dc 130 dB
CMRR Common-mode rejection ratio RS = 0Ω, VCM = ±11.25V INA126P
INA2126P		 83 94 dB
INA126U/E
INA2126U/E		 80 94
INA126PA/UA/EA
INA2126PA/UA/EA		 74 83
INPUT BIAS CURRENT
IB Input bias current INA126P/U/E
INA2126P/U/E		 ±10 ±25 nA
INA126PA/UA/EA
INA2126PA/UA/EA 		±10 ±50
Input bias current drift TA = –40°C to +85°C ±30 pA/℃
IOS Input offset current INA126P/U/E
INA2126P/U/E		 ±0.5 ±2 nA
INA126PA/UA/EA
INA2126PA/UA/EA		 ±0.5 ±5 nA
Input offset current drift TA = –40°C to +85°C ±10 pA/℃
GAIN
Gain equation 5 + (80 kΩ / RG) V/V
G Gain 5 10000 V/V
GE Gain error G = 5 , VO = ±14V INA126P/U/E
INA2126P/U/E		 ±0.02 ±0.1 %
INA126PA/UA/EA
INA2126PA/UA/EA		 ±0.02 ±0.18
G = 100, VO = ±12V INA126P/U/E
INA2126P/U/E		 ±0.2 ±0.5
INA126PA/UA/EA
INA2126PA/UA/EA		 ±0.2 ±1
Gain drift(2) TA = –40°C to +85°C G = 5 ±2 ±10 ppm/°C
G = 100 ±25 ±100
Gain nonlinearity G = 100, VO = ±14V ±0.002 ±0.012 %
NOISE
eN Voltage noise f = 1kHz CSO: SHE 35 nV/√Hz
CSO: TID 24
f = 100Hz CSO: SHE 35
CSO: TID 24
fB = 10Hz CSO: SHE 45
CSO: TID 24
fB = 0.1Hz to 10Hz CSO: SHE 0.7 µVPP
CSO: TID 0.5
In Current noise f = 1 kHz 160 fA/√Hz
fB = 0.1Hz to 10Hz 7.3 pAPP
OUTPUT
Positive output voltage swing (V+) – 0.9 (V+) – 0.75 V
Negative output voltage swing (V–) + 0.95 (V–) + 0.8 V
ISC Short-circuit current Continuous to VS / 2 ±5 mA
CL Load capacitance Stable operation 1000 pF
FREQUENCY RESPONSE
BW Bandwidth, –3dB G = 5 CSO: SHE 200 kHz
CSO: TID 250
G = 100 CSO: SHE 9
CSO: TID 10
G = 500 CSO: SHE 1.8
CSO: TID 2
SR Slew rate G = 5, VO = ±10V 0.4 V/µs
tS Settling time To 0.01%, VSTEP = 10V G = 5 30 µs
G = 100 160
G = 500 1500
Overload recovery 50% input overload 4 µs
POWER SUPPLY
IQ Quiescent current (per channel) IO = 0mA ±175 ±200 µA
(1) Input voltage range of the instrumentation amplifier input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See Typical Characteristic curves.
(2) The values specified for G > 5 do not include the effects of the external gain-setting resistor, RG.