SLLSFN5A June   2023  – February 2024 ISO1228

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—DC Specification
    10. 5.10 Switching Characteristics—AC Specification
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Surge Protection
      2. 7.3.2  Field Side LED Indication
      3. 7.3.3  Serial and Parallel Output option
      4. 7.3.4  Cyclic Redundancy Check (CRC)
      5. 7.3.5  FAULT Indication
      6. 7.3.6  Digital Low Pass Filter
      7. 7.3.7  SPI Register Map
      8. 7.3.8  SPI Interface Timing - Non-Daisy Chain
      9. 7.3.9  SPI Interface Timing - Daisy Chain
      10. 7.3.10 SPI Interface Timing - Burst Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Sinking Type Digital Inputs
      2. 8.2.2 Sourcing Type Digital Inputs
      3. 8.2.3 Design Requirements
        1. 8.2.3.1 Detailed Design Procedure
          1. 8.2.3.1.1 Current Limit
          2. 8.2.3.1.2 Voltage Thresholds
          3. 8.2.3.1.3 Wire-Break Detection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10 Switching Characteristics—AC Specification

(Over recommended operating conditions unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER-UP TIMING
TPWRUP Time taken for the device to power up, and start communication after VCC1 and AVCC are above their UVLO levels.  VCC1 and AVCC are ramped up together. 140 200 µs
TFILTAVCC Internal de-glitch filter on AVCC AVCC supply dip to corresponding UVLO- thresholds with 10 ns rise/fall times. 3 5 7 µs
TFILTVCC1 Internal de-glitch filter on VCC1 - recovery time VCC1 supply dip to UVLO- thresholds with 10 ns rise/fall times upto 9us. Time needed by device to be functional again 1 4 7 µs
PROPAGATION DELAY AND CMTI
tr, tf Output signal rise and fall time, OUTx pins CLOAD = 15 pF, 24-VP-P clock signal on IN pin with 10-ns rise and fall time, RTHR = 0 Ω. Parallel output mode.
F1=low, F0=low; Filter Register setting: 0xxx		 3 ns
tPLH Propagation delay time for low to high transition 24-VPk-Pk clock signal on IN pin with 10-ns rise and fall time, RTHR = 0 Ω. Parallel output mode.
F1=low, F0=low; Filter Register setting: 0xxx		 780 ns
tPHL Propagation delay time for high to low transition 24-VP-P clock signal on IN pin with 10-ns rise and fall time, RTHR = 0 Ω. Parallel output mode.
F1=low, F0=low; Filter Register setting: 0xxx		 900 ns
tsk(p) Pulse skew |tPHL - tPLH| 24-VP-P clock signal on IN pin with 10-ns rise and fall time, RTHR = 0 Ω. Parallel output mode. 335 ns
tUI Minimum pulse width Parallel output mode.
F1=low, F0=low; Filter Register setting: 0xxx		 660 ns
tPHZ Disable propagation delay, high-to-high impedance output VIN = 24 V, Pull down resistor of 1kΩ on OUTx. Parallel output mode 30 65 ns
tPLZ Disable propagation delay, low-to-high impedance output VIN = 0 V, Pull up resistor of 1kΩ on OUTx. Parallel output mode 30 60 ns
tPZH Enable propagation delay, high impedance-to-high output VIN = 24 V, Pull down resistor of 1kΩ on OUTx. Parallel output mode 3 5 µs
tPZL Enable propagation delay, high impedance-to-low output VIN = 0 V, Pull up resistor of 1kΩ on OUTx. Parallel output mode 1.5 2.6 µs
CMTI Common mode transient immunity F1=low, F0=low; Filter Register setting: 0xxx 50 75 kV/µs
DIGITAL LOW PASS FILTER
TFILT Input Digital Low Pass Filter Averaging Time

 F1=low, F0=low; Filter Register setting: 0xxx 0 ns
F1=low, F0=float; Filter Register setting: 1000 1 µs
F1=low, F0=high; Filter Register setting: 1001 8 µs
F1=float, F0=low; Filter Register setting: 1010  200 µs
F1=float, F0=float; Filter Register setting: 1011 1 ms
F1=float, F0=high; Filter Register setting: 1100 2.5 ms
F1=high, F0=low; Filter Register setting: 1101 10 ms
F1=high, F0=float; Filter Register setting: 1110 30 ms
F1=high, F0=high; Filter Register setting: 1111  100 ms
TFILTWB Input Filter for Wire-break Detection 30 ms
SPI TIMING - 2.25 V to 5.5 V
FSCLK SCLK Frequency, VCC1 = 2.25 V to 5.5 V 25 MHz
TSCLK SCLK Bit Period 40 ns
TSCLKH SCLK High Pulse Width 20 ns
TSCLKL SCLK Low Pulse Width 20 ns
TDO SCLK output to SDO valid 4.5 12.5 ns
TCSW Chip Select 'High' Pulse Width  250 ns
TCSCLK Time from nCS low to SCLK first rising edge 20 ns
TCLKCS Time from SCLK last falling edge to nCS high 10 ns
TCSDOV Time from nCS low to SDO first data valid 10 ns
TCSDOZ Time from nCS high to SDO hi-Z 15 ns
TSDISU Setup time SDI to SCLK rising edge 10 ns
TSDIH Hold time SCLK rising edge to SDI 10 ns
TFLTW nFAULT min low time after last fault de-assertion (unless fault register read)  9 µs
TSRSTNCS Time from nSRST high (de-assertion) to CS low (assertion) 150 ns
SPI TIMING - 1.71 V to 2.25 V
FSCLK SCLK Frequency, VCC1 = 1.71 V to 2.25 V 15 MHz
TSCLK SCLK Bit Period 66.67 ns
TSCLKH SCLK High Pulse Width 33.33 ns
TSCLKL SCLK Low Pulse Width 33.33 ns
TDO SCLK output to SDO valid 7 21.5 ns
TCSW Chip Select 'High' Pulse Width  390 ns
TCSCLK Time from nCS low to SCLK first rising edge 20 ns
TCLKCS Time from SCLK last falling edge to nCS high 10 ns
TCSDOV Time from nCS low to SDO first data valid 20 ns
TCSDOZ Time from nCS high to SDO hi-Z 20 ns
TSDISU Setup time SDI to SCLK rising edge 10 ns
TSDIH Hold time SCLK rising edge to SDI 10 ns
TFLTW nFAULT min low time after last fault de-assertion (unless fault register read)  9 µs
TSRSTNCS Time from nSRST high (de-assertion) to CS low (assertion) 200 ns
TCOMMSEL1 Time from COMM_SEL low to high to first valid nCS 300 ns
TCOMMSEL2 Time from COMM_SEL high to low to valid OUTx 60 ns