SWRS219F October   2018  – April 2025 IWR6443 , IWR6843

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions - Digital
      2. 6.2.2 Signal Descriptions - Analog
    3. 6.3 Pin Attributes
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  Power Save Mode
    9. 7.9  RF Specification
    10. 7.10 CPU Specifications
    11. 7.11 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    12. 7.12 Timing and Switching Characteristics
      1. 7.12.1  Power Supply Sequencing and Reset Timing
      2. 7.12.2  Input Clocks and Oscillators
        1. 7.12.2.1 Clock Specifications
      3. 7.12.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.3.1 Peripheral Description
        2. 7.12.3.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.3.2.1 SPI Timing Conditions
          2. 7.12.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
          3. 7.12.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
        3. 7.12.3.3 SPI Peripheral Mode I/O Timings
          1. 7.12.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
        4. 7.12.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 7.12.4  LVDS Interface Configuration
        1. 7.12.4.1 LVDS Interface Timings
      5. 7.12.5  General-Purpose Input/Output
        1. 7.12.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 7.12.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.6.1 Dynamic Characteristics for the CANx TX and RX Pins
      7. 7.12.7  Serial Communication Interface (SCI)
        1. 7.12.7.1 SCI Timing Requirements
      8. 7.12.8  Inter-Integrated Circuit Interface (I2C)
        1. 7.12.8.1 I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
      9. 7.12.9  Quad Serial Peripheral Interface (QSPI)
        1. 7.12.9.1 QSPI Timing Conditions
        2. 7.12.9.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
        3. 7.12.9.3 QSPI Switching Characteristics
      10. 7.12.10 ETM Trace Interface
        1. 7.12.10.1 ETMTRACE Timing Conditions
        2. 7.12.10.2 ETM TRACE Switching Characteristics
      11. 7.12.11 Data Modification Module (DMM)
        1. 7.12.11.1 DMM Timing Requirements
      12. 7.12.12 JTAG Interface
        1. 7.12.12.1 JTAG Timing Conditions
        2. 7.12.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.12.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Host Interface
      4. 8.3.4 Main Subsystem Cortex-R4F
      5. 8.3.5 DSP Subsystem
      6. 8.3.6 Hardware Accelerator
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Channels (Service) for User Application
        1. 8.4.1.1 GP-ADC Parameter
    5. 8.5 Boot Modes
      1. 8.5.1 Flashing Mode
      2. 8.5.2 Functional Mode
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
      1. 9.1.1 Error Signaling Module
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for ABL, 10.4 × 10.4 mm

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Power Consumption Summary

Table 7-3 and Table 7-4 summarize the power consumption at the power terminals.

Table 7-3 Maximum Current Ratings at Power Terminals
PARAMETER SUPPLY NAME DESCRIPTION MIN TYP MAX UNIT
Current consumption(1) VDDIN, VIN_SRAM, VNWA Total current drawn by all nodes driven by 1.2V rail 1000 mA
VIN_13RF1, VIN_13RF2 Total current drawn by all nodes driven by 1.3V rail (or 1V rail in LDO Bypass mode), when only 2 transmitters are used.(2) 2000
VIOIN_18, VIN_18CLK, VIOIN_18DIFF, VIN_18BB, VIN_18VCO Total current drawn by all nodes driven by 1.8V rail 850
VIOIN Total current drawn by all nodes driven by 3.3V rail(3) 50
(1) The specified current values are at typical supply voltage level.
(2) Simultaneous 3 Transmitter operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to be fed on the VOUT_PA pin. In this case, the peak 1-V supply current goes up to 2500 mA. To enable the LDO bypass mode, see the Interface Control document in the mmWave Device Firmware Package.
(3) The exact VIOIN current depends on the peripherals used and their frequency of operation.
Table 7-4 Average Power Consumption at Power Terminals
PARAMETER CONDITION DESCRIPTION MIN TYP MAX UNIT
Average power consumption 1.0-V internal LDO bypass mode 24% duty cycle 1TX, 4RX Regular power ADC mode 6.4 Msps complex transceiver, 13.13-ms frame, 64 chirps, 256 samples/chirp, 8.5-µs interchirp time, DSP + Hardware accelerator active 1.19 W
2TX, 4RX(1) 1.25
48% duty cycle 1TX, 4RX Regular power ADC mode 6.4 Msps complex transceiver, 13.13-ms frame, 64 chirps, 256 samples/chirp, 8.5-µs interchirp time, DSP + Hardware accelerator active 1.62
2TX, 4RX(1) 1.75
(1) Two TX antennas are on simultaneously.