SNVS397F September   2005  – December 2025 LM5005

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Voltage Start-Up Regulator
      2. 6.3.2 Shutdown and Standby
      3. 6.3.3 Oscillator and Synchronization Capability
      4. 6.3.4 Error Amplifier and PWM Comparator
      5. 6.3.5 RAMP Generator
      6. 6.3.6 Current Limit
      7. 6.3.7 Soft-Start Capability
      8. 6.3.8 MOSFET Gate Driver
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Light-Load Operation
      4. 6.4.4 Thermal Shutdown Protection
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reducing Bias Power Dissipation
      2. 7.1.2 Input Voltage UVLO Protection
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design With WEBENCH® Tools
        2. 7.2.2.2  Frequency Set Resistor (RT)
        3. 7.2.2.3  Inductor (LF)
        4. 7.2.2.4  Ramp Capacitor (CRAMP)
        5. 7.2.2.5  Output Capacitors (COUT)
        6. 7.2.2.6  Schottky Diode (DF)
        7. 7.2.2.7  Input Capacitors (CIN)
        8. 7.2.2.8  VCC Capacitor (CVCC)
        9. 7.2.2.9  Bootstrap Capacitor (CBST)
        10. 7.2.2.10 Soft Start Capacitor (CSS)
        11. 7.2.2.11 Feedback Resistors (RFB1 and RFB2)
        12. 7.2.2.12 RC Snubber (RS and CS)
        13. 7.2.2.13 Compensation Components (RC1, CC1, CC2)
        14. 7.2.2.14 Bill of Materials
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout for EMI Reduction
        2. 7.4.1.2 Thermal Design
        3. 7.4.1.3 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Development Support
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
    3. 8.3 Documentation Support
      1. 8.3.1 Related Documentation
        1. 8.3.1.1 PCB Layout Resources
        2. 8.3.1.2 Thermal Design Resources
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

LM5005 PWP Package20-pin HTSSOPTop View Figure 4-1 PWP Package20-pin HTSSOPTop View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 10 G Analog ground. Internal reference for the regulator control functions.
BST 20 P Boost input for bootstrap capacitor. Connect an external capacitor between the BST and SW pins. A 22nF ceramic capacitor is recommended. The capacitor is charged from VCC through an internal bootstrap diode during the off-time of the buck switch when the SW-node voltage is low.
COMP 6 O Output of the internal error amplifier, the loop compensation network must be connected between this pin and the FB pin.
EP — P Exposed pad. Exposed metal pad on the underside of the device. Connect this pad to the PCB ground plane to assist with heat spreading.
FB 7 I Feedback signal from the regulated output. This pin is connected to the inverting input of the internal error amplifier. The regulation threshold is 1.225V.
IS 15, 16 P Current sense. Current measurement connection for the freewheeling Schottky diode. An internal sense resistor and a sample-and-hold circuit sense the diode current near the conclusion of the off-time. This current measurement provides the DC level of the emulated current ramp.
OUT 12 I Output voltage connection. Connect directly to the regulated output voltage.
PGND 13, 14 G Power ground. Low-side reference for the integrated PRE switch and the IS current sense resistor.
PRE 19 P Precharge assist for the bootstrap capacitor. Connect this open-drain output to the SW pins to aid charging the bootstrap capacitor during light-load conditions or in applications where the output may be precharged before the LM5005 is enabled. An internal precharge MOSFET is turned on for 250ns each cycle just prior to the on-time interval of the buck switch.
RAMP 9 I Ramp control signal. An external capacitor connected between RAMP and AGND pins sets the ramp slope used for emulated peak current-mode control. Recommended capacitance range is 50pF to 2nF.
RT 8 I Internal oscillator frequency set input. The internal oscillator is set with a single resistor connected between RT and AGND pins. The recommended switching frequency range is 50kHz to 500kHz.
SD 2 I Shutdown or UVLO input. If the SD pin voltage is below 0.7V, the regulator is in a low power state. If the SD pin voltage is between 0.7V and 1.225V, the regulator is in standby mode. If the SD pin voltage is above 1.225V, the regulator is operational. Use an external voltage divider to set a line undervoltage shutdown threshold. If the SD pin is left open circuit, a 5µA pullup current source configures the regulator as fully operational.
SS 11 I Soft-start. An external capacitor and an internal 10-µA current source set the ramp rate for the rise of the error amplifier's reference. The SS pin is held low during standby, VCC UVLO and thermal shutdown.
SW 17, 18 P Switching node. The source terminal of the internal buck switch. Connect the SW pin to the external Schottky diode and to the buck inductor.
SYNC 5 I/O Oscillator synchronization input or output. The internal oscillator can be synchronized to an external clock with an external pulldown device. Multiple LM5005 regulators can be synchronized together by connection of their SYNC pins.
VCC 1 I Output of the bias regulator. VCC tracks VIN up to 9V. Beyond 9V, VCC is regulated to 7V. A 0.1µF to 1µF ceramic decoupling capacitor is required. An external voltage (7.5V to 14V) can be applied to this pin to reduce internal power dissipation.
VIN 3, 4 P Input supply voltage, nominal operating range: 7V to 75V.
(1) G = ground, I = input, O = output, P = power, I/O = bidirectional