SNVS397F September   2005  – December 2025 LM5005

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Voltage Start-Up Regulator
      2. 6.3.2 Shutdown and Standby
      3. 6.3.3 Oscillator and Synchronization Capability
      4. 6.3.4 Error Amplifier and PWM Comparator
      5. 6.3.5 RAMP Generator
      6. 6.3.6 Current Limit
      7. 6.3.7 Soft-Start Capability
      8. 6.3.8 MOSFET Gate Driver
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Light-Load Operation
      4. 6.4.4 Thermal Shutdown Protection
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reducing Bias Power Dissipation
      2. 7.1.2 Input Voltage UVLO Protection
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design With WEBENCH® Tools
        2. 7.2.2.2  Frequency Set Resistor (RT)
        3. 7.2.2.3  Inductor (LF)
        4. 7.2.2.4  Ramp Capacitor (CRAMP)
        5. 7.2.2.5  Output Capacitors (COUT)
        6. 7.2.2.6  Schottky Diode (DF)
        7. 7.2.2.7  Input Capacitors (CIN)
        8. 7.2.2.8  VCC Capacitor (CVCC)
        9. 7.2.2.9  Bootstrap Capacitor (CBST)
        10. 7.2.2.10 Soft Start Capacitor (CSS)
        11. 7.2.2.11 Feedback Resistors (RFB1 and RFB2)
        12. 7.2.2.12 RC Snubber (RS and CS)
        13. 7.2.2.13 Compensation Components (RC1, CC1, CC2)
        14. 7.2.2.14 Bill of Materials
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout for EMI Reduction
        2. 7.4.1.2 Thermal Design
        3. 7.4.1.3 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Development Support
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
    3. 8.3 Documentation Support
      1. 8.3.1 Related Documentation
        1. 8.3.1.1 PCB Layout Resources
        2. 8.3.1.2 Thermal Design Resources
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

PC board layout is an important and critical part of any DC-DC converter design. The performance of any switching converter depends as much upon the layout of the PCB as the component selection. Poor layout disrupts the performance of a switching converter and surrounding circuitry by contributing:

  • EMI
  • Ground bounce
  • Conduction loss in the traces
  • Thermal problems

Erroneous signals can reach the DC-DC converter, possibly resulting in poor regulation or instability. There are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade the power-supply performance.

The following guidelines serve to help users to design a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

  1. In a buck regulator there are two critical current conduction loops. The first loop starts from the input capacitors to the LM5005 VIN pins, to the SW pin, to the inductor and then out to the load. The second loop starts from the output capacitors return terminals, to the LM5005 PGND pins, to the IS pins, to the freewheeling diode anode, to the inductor and then out to the load. Minimizing the effective area of these two loops reduces the stray inductance and minimizes noise and possible erratic operation.
  2. Place the input capacitors close to the LM5005 VIN pins and exposed pad that connects to the PGND pins. Place the inductor as close as possible to the SW pins and output capacitors. As described further in PCB Layout for EMI Reduction, the placement serves to minimize the area of switching current loops and reduce the resistive loss of the high current path. An excellent choice is to use a ground plane on the top layer that connects the PGND pins, the exposed pad of the device, and the return terminals of the input and output capacitors. For more details, see the board layout detailed in the AN-1748 LM5005 Evaluation Board user's guide .
  3. Minimize the copper area of the switch node. Route the two SW pins on a single top-layer plane to the inductor terminal using a wide trace to minimize conduction loss. The inductor can be placed on the bottom side of the PCB relative to the LM5005, but take care to avoid any coupling of the inductors magnetic field to sensitive feedback or compensation traces.
  4. Use a solid ground plane on layer two of the PCB, particularly underneath the LM5005 and power stage components. This plane functions as a noise shield and also as a heat dissipation path.
  5. Make input and output power bus connections as wide and short as possible to reduce voltage drops on the input and output of the converter and to improve efficiency. Use copper planes on top to connect the multiple VIN pins and PGND pins together.
  6. Provide enough PCB area for proper heat-sinking. As stated in Thermal Design, use enough copper area to provide a low RθJA commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB layers with two ounce copper thickness and no less than one ounce. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers as recommended, connect these thermal vias to the inner layer heat-spreading ground planes.
  7. Route the sense trace from the VOUT point of regulation to the feedback resistors away from the SW pins and inductor to avoid contaminating this feedback signal with switching noise. This routing is most important when high resistances are used to set the output voltage. Routing the feedback trace on a different layer than the inductor and SW node trace is recommended such that a ground plane exists between the sense trace and inductor or SW node polygon to provide further cancellation of EMI on the feedback trace.
  8. If voltage accuracy at the load is important, confirm that the feedback voltage sense is made directly at the load terminals. Doing so corrects for voltage drops in the PCB planes and traces and provides excellent output voltage set-point accuracy and load regulation. Place the feedback resistor divider closer to the FB pin, rather than close to the load, because the FB node is the input to the error amplifier and is thus noise sensitive.
  9. COMP is a also noise-sensitive node. Place the compensation components as close as possible to the FB and COMP pins.
  10. Place the components for RT, CSS, CRAMP and CVCC close to the respective pins. Connect all of the signal components ground return connections directly to the LM5005's AGND pin. Connect the AGND and PGND pins together at the LM5005's exposed pad using the topside copper area covering the entire underside of the device. Connect several vias within this underside copper area to the PCB internal ground plane.
  11. See Related Documentation for additional important guidelines.