SNVS397F September   2005  – December 2025 LM5005

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Voltage Start-Up Regulator
      2. 6.3.2 Shutdown and Standby
      3. 6.3.3 Oscillator and Synchronization Capability
      4. 6.3.4 Error Amplifier and PWM Comparator
      5. 6.3.5 RAMP Generator
      6. 6.3.6 Current Limit
      7. 6.3.7 Soft-Start Capability
      8. 6.3.8 MOSFET Gate Driver
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Standby Mode
      3. 6.4.3 Light-Load Operation
      4. 6.4.4 Thermal Shutdown Protection
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reducing Bias Power Dissipation
      2. 7.1.2 Input Voltage UVLO Protection
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design With WEBENCH® Tools
        2. 7.2.2.2  Frequency Set Resistor (RT)
        3. 7.2.2.3  Inductor (LF)
        4. 7.2.2.4  Ramp Capacitor (CRAMP)
        5. 7.2.2.5  Output Capacitors (COUT)
        6. 7.2.2.6  Schottky Diode (DF)
        7. 7.2.2.7  Input Capacitors (CIN)
        8. 7.2.2.8  VCC Capacitor (CVCC)
        9. 7.2.2.9  Bootstrap Capacitor (CBST)
        10. 7.2.2.10 Soft Start Capacitor (CSS)
        11. 7.2.2.11 Feedback Resistors (RFB1 and RFB2)
        12. 7.2.2.12 RC Snubber (RS and CS)
        13. 7.2.2.13 Compensation Components (RC1, CC1, CC2)
        14. 7.2.2.14 Bill of Materials
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout for EMI Reduction
        2. 7.4.1.2 Thermal Design
        3. 7.4.1.3 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Development Support
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
    3. 8.3 Documentation Support
      1. 8.3.1 Related Documentation
        1. 8.3.1.1 PCB Layout Resources
        2. 8.3.1.2 Thermal Design Resources
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5 RAMP Generator

The ramp signal used in the pulse width modulator for current-mode control is typically derived directly from the buck switch current. This switch current corresponds to the positive slope portion of the output inductor current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feedforward compensation. The disadvantage of using the buck switch current signal for PWM control is the large leading-edge spike due to circuit parasitics that must be filtered or blanked. Also, the current measurement can introduce significant propagation delays. The filtering, blanking time and propagation delay limit the minimum achievable pulse-width. In applications where the input voltage can be relatively large in comparison to the output voltage, controlling small pulse-widths and duty cycles is necessary for regulation.

The LM5005 uses a unique ramp generator, which does not actually measure the buck switch current but rather reconstructs the current signal. Reconstructing or emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading-edge spikes and measurement or filtering delays. The current reconstruction is comprised of two elements: a sample-and-hold DC level and an emulated current ramp.

LM5005 Emulated Current-Sense Ramp WaveformFigure 6-5 Emulated Current-Sense Ramp Waveform

The sample-and-hold DC level illustrated in Figure 6-5 is derived from a measurement of the current flowing in the freewheeling Schottky diode. Connect the anode terminal of the freewheeling diode to the LM5005's IS pin. The diode current flows through an internal current sense resistor between the IS and PGND pins. The voltage level across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode current sensing and sample-and-hold provide the DC level for the reconstructed current signal. The positive slope inductor current ramp is emulated by an internal voltage-controlled current source and an external capacitor connected between the RAMP and AGND pins. The ramp current source that emulates the inductor current is a function of the input and output voltages given by Equation 2.

Equation 2. I R A M P = 5 μ A × V I N - V O U T + 25 μ A

Proper selection of the RAMP capacitor depends upon the selected output inductance. Select the capacitance of CRAMP using Equation 3.

Equation 3. C R A M P = L F × 10 - 5

where

  • LF is the output inductance in Henrys

With this value, the scale factor of the emulated current ramp is approximately equal to the scale factor of the DC level sample-and-hold (0.5V/A). Place the CRAMP capacitor close to the LM5005's RAMP and AGND pins.

For duty cycles greater than 50%, peak current-mode control circuits are subject to subharmonic oscillation. Subharmonic oscillation is normally characterized by observing alternating wide and narrow pulses of the switch-node voltage waveform. Adding a fixed-slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 25µA of offset current provided from the emulated current source adds some fixed slope to the ramp signal. In some high output voltage and high duty cycle applications, additional slope can be required. In these applications, add a pullup resistor between the VCC and RAMP pins to increase the ramp slope compensation.

For VOUT > 7.5V, calculate the optimal slope current with Equation 4.

Equation 4. I O S = V O U T × 5 μ A / V

For example, at VOUT = 10V, IOS = 50µA.

Install a resistor from the RAMP pin to VCC using Equation 5.

Equation 5. R R A M P = V V C C I O S - 25 μ A
LM5005 Connection of External Ramp Resistor to VCC when VOUT > 7.5VFigure 6-6 Connection of External Ramp Resistor to VCC when VOUT > 7.5V