The device includes programmable hiccup mode overload protection which is enabled when a capacitor (C_RES) is connected to the RES pin in buck configuration. The hiccup mode overload protection is disabled in boost configuration or RES is connected to VDD during initial power-on.

In normal operation, C_RES is discharged to ground and an internal fault counter counts the clocks when cycle-by-cycle current limiting occurs. When the fault counter detects 256 cycles of switching with current limit on any buck channel, an internal hiccup mode off-timer forces the applicable channel to stop switching and starts sourcing 20 μA of current (I_RES) into C_RES. During this hiccup mode overload protection, the off-time before the channel restart (T_RES) is programmed by C_RES. During T_RES, the HO and the LO outputs are disabled and C_SS is charged by I_RES. When the RES pin voltage reaches the RES threshold (V_RESTH) , C_RES is discharged by an internal RES pull-down switch, and C_SS begins to charge with 30us delay. The 256 cycle fault counter is reset if eight consecutive switching cycles occur without current limit.

Figure 8-20 Hiccup Mode Overload Protection (Single Channel Fault)

The device provides an independent fault counter per channel, but the RES pin is shared by all channels. The device allows that one channel is in the hiccup mode off while the other channels operate normally. In the event that multiple channels are in a fault condition, the last fault counter pulls the RES pin low and starts the RES capacitor charging cycle. Then, the multiple channels which are in the fault condition restart together when the RES pin voltage reaches V_RESTH. If CH2 and CH3 are configured as an interleaved dual-phase buck, the fault counters count the fault independently, but both CH2 and CH3 stop switching and restart together.

Figure 8-21 Hiccup Mode Overload Protection (Multiple Channel Faults)

The hiccup mode protection is also programmed during the initial configuration time. If RES is connected to VDD during the initial configuration time, the internal fault counter is disabled and the device operates with non-hiccup mode cycle-by-cycle current limit. If RES is connected to AGND, the applicable channel that detects 256 cycles of current limiting stops switching and then never restarts until the applicable channel's EN pin is toggled.

Figure 8-22 Hiccup Mode Configuration