SNVSBZ3 June   2021 LM5168-Q1

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Internal Soft Start
      4. 8.3.4  On-Time Generator
      5. 8.3.5  Current Limit
      6. 8.3.6  N-Channel Buck Switch and Driver
      7. 8.3.7  Synchronous Rectifier
      8. 8.3.8  Enable/Undervoltage Lockout (EN/UVLO)
      9. 8.3.9  Power Good (PGOOD)
      10. 8.3.10 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 Sleep Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency (RT)
        2. 9.2.2.2  Transformer Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Secondary Output Diode
        5. 9.2.2.5  Regulation Comparator
        6. 9.2.2.6  Input Capacitor
        7. 9.2.2.7  Type-3 Ripple Network
        8. 9.2.2.8  Minimum Secondary Output Load
        9. 9.2.2.9  Example Design Summary
        10. 9.2.2.10 Thermal Considerations
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact PCB Layout for EMI Reduction
      2. 11.1.2 Feedback Resistors
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Current Limit

The PFM variant of the LM516x-Q1 manages overcurrent conditions with cycle-by-cycle current limiting of the peak inductor current. The current sensed in the high-side MOSFET is compared every switching cycle to the current limit threshold (0.84 A or 0.42 A). To protect the converter from potential current runaway conditions, the LM516x-Q1 includes a foldback valley current limit feature, set at 0.67 A for the LM5169-Q1 and 0.34 A for LM5168-Q1, that is enabled if a peak current limit is detected. As shown in Figure 8-1, if the peak current in the high-side MOSFET exceeds 0.84 A for the LM5169-Q1 and 0.42 A for the LM5168-Q1 (typical), the present cycle is immediately terminated regardless of the programmed on time (tON), the high-side MOSFET is turned off and the foldback valley current limit is activated. The low-side MOSFET remains on until the inductor current drops below this foldback valley current limit, after which the next on-pulse is initiated. This method folds back the switching frequency to prevent overheating and limits the average output current to less than 0.65 A for LM5169-Q1 and 0.3 A for LM5168-Q1 to ensure proper short-circuit and heavy-load protection.

GUID-D2461D78-CDF2-46E5-B34B-3424EBBE8EF8-low.gifFigure 8-1 Current Limit Timing Diagram

Current is sensed after a leading-edge blanking time following the high-side MOSFET turnon transition. The propagation delay of the current limit comparator is 100 ns. During high step-down conditions when the on-time is less than 100 ns, a back-up peak current limit comparator in the low-side FET also set at 0.84 A, or 0.42 A enables the foldback valley current limit set at 0.67 A or 0.34 A. This innovative current limit scheme enables ultra-low duty-cycle operation, permitting large step-down voltage conversions while ensuring robust protection of the converter.

The FPWM variant of the device implements a current limit off-timer and hiccup protection. If the current in the high-side MOSFET exceeds IHS_PK(OC), the high-side MOSFET is immediately turned off and a non-resettable off-timer is initiated. The length of the off time is controlled by the feedback voltage and the input voltage. The off-timer ensures safe short circuit operation in fly-buck configuration. An overload current on the secondary output can result in the secondary voltage collapsing while the primary voltage remains in regulation. This results in a possible condition where the secondary output voltage will not recover after the overload condition. Hiccup protection ensures a soft-start counter will enable both the secondary and primary output voltages to recover properly after an overcurrent event is detected for 16 consecutive current limit cycles. After four cycles without current limit detection, restart the hiccup protection counter. The LM516x-Q1 will attempt soft start after a "hiccup period" of 64 ms.