SNVSBZ3 June   2021 LM5168-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Internal Soft Start
      4. 8.3.4  On-Time Generator
      5. 8.3.5  Current Limit
      6. 8.3.6  N-Channel Buck Switch and Driver
      7. 8.3.7  Synchronous Rectifier
      8. 8.3.8  Enable/Undervoltage Lockout (EN/UVLO)
      9. 8.3.9  Power Good (PGOOD)
      10. 8.3.10 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 Sleep Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Switching Frequency (RT)
        2.  Transformer Selection
        3.  Output Capacitor Selection
        4.  Secondary Output Diode
        5.  Regulation Comparator
        6.  Input Capacitor
        7.  Type-3 Ripple Network
        8.  Minimum Secondary Output Load
        9.  Example Design Summary
        10. Thermal Considerations
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact PCB Layout for EMI Reduction
      2. 11.1.2 Feedback Resistors
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade the power supply performance.

  1. To help eliminate these problems, bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with a high-quality dielectric. Place CIN as close as possible to the LM516x-Q1 VIN and GND pins. Grounding for both the input and output capacitors must consist of localized top-side planes that connect to the GND pin and GND PAD.
  2. Minimize the loop area formed by the input capacitor connections to the VIN and GND pins.
  3. Locate the inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive capacitive coupling.
  4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
  5. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
  6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, and enable components to the ground plane. This prevents any switched or load currents from flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior.
  7. Make VIN, VOUT, and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
  8. Minimize trace length to the FB pin. Place both feedback resistors, RFB1 and RFB2, close to the FB pin. Place CFF (if used) directly in parallel with RFB1. If output set-point accuracy at the load is important, connect the VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on the other side of a grounded shielding layer.
  9. The RT pin is sensitive to noise. Thus, locate the RT resistor as close as possible to the device and route with minimal lengths of trace. The parasitic capacitance from RT to GND must not exceed 20 pF.
  10. Provide adequate heat sinking for the LM516x-Q1 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper layers, these thermal vias must also be connected to inner layer heat-spreading ground planes.