SNVSBW1B December   2021  – October 2023 LM63460-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1. 6.1 Wettable Flanks
    2. 6.2 Pinout Design for Clearance and FMEA
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Systems Characteristics
    8. 7.8 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Output Voltage Setpoint (FB)
      3. 8.3.3  Precision Enable and Input Voltage UVLO (EN/SYNC)
      4. 8.3.4  Frequency Synchronization (EN/SYNC)
      5. 8.3.5  Clock Locking
      6. 8.3.6  Adjustable Switching Frequency (RT)
      7. 8.3.7  Power-Good Monitor (PGOOD)
      8. 8.3.8  Bias Supply Regulator (VCC, BIAS)
      9. 8.3.9  Bootstrap Voltage and UVLO (CBOOT)
      10. 8.3.10 Spread Spectrum
      11. 8.3.11 Soft Start and Recovery From Dropout
      12. 8.3.12 Overcurrent and Short-Circuit Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 AUTO Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Foldback
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – Automotive Synchronous Buck Regulator at 2.1 MHz
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Setting the Output Voltage
          3. 9.2.1.2.3  Choosing the Switching Frequency
          4. 9.2.1.2.4  Inductor Selection
          5. 9.2.1.2.5  Output Capacitor Selection
          6. 9.2.1.2.6  Input Capacitor Selection
          7. 9.2.1.2.7  Bootstrap Capacitor
          8. 9.2.1.2.8  VCC Capacitor
          9. 9.2.1.2.9  BIAS Power Connection
          10. 9.2.1.2.10 Feedforward Network
          11. 9.2.1.2.11 Input Voltage UVLO
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Automotive Synchronous Buck Regulator at 400 kHz
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Standby Mode

The internal LDO has a lower enable threshold than the output of the converter. When the EN/SYNC pin voltage is above 1.1 V (maximum) and below the precision enable threshold, the internal LDO regulates the VCC voltage at 3.3 V typical. The precision enable circuitry is ON after VCC is above its UVLO. The internal power MOSFETs remain off unless the voltage on EN/SYNC goes above its precision enable threshold. The converter also employs UVLO protection. If the VCC voltage is below its UVLO level, the output of the converter is turned off.