SNOSDE6C December   2022  – August 2025 LM74900-Q1 , LM74910-Q1 , LM74910H-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump
      2. 8.3.2 Dual Gate Control (DGATE, HGATE)
        1. 8.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 8.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 8.3.3 Overcurrent Protection (CS+, CS-, ILIM, IMON, TMR)
        1. 8.3.3.1 Pulse Overload Protection, Circuit Breaker
        2. 8.3.3.2 Overcurrent Protection With Latch-Off
        3. 8.3.3.3 Short Circuit Protection (ISCP)
        4. 8.3.3.4 Analog Current Monitor Output (IMON)
      4. 8.3.4 Undervoltage Protection, Overvoltage Protection, and Battery Voltage Sensing (UVLO, OV, SW)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Ultra Low IQ Shutdown (EN)
      2. 8.4.2 Low IQ SLEEP Mode (SLEEP)
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12V Battery Protection
      2. 9.2.2 Automotive Reverse Battery Protection
        1. 9.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 9.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 9.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Design Considerations
        2. 9.2.3.2 Charge Pump Capacitance VCAP
        3. 9.2.3.3 Input and Output Capacitance
        4. 9.2.3.4 Hold-Up Capacitance
        5. 9.2.3.5 Selection of Current Sense Resistor, RSNS
        6. 9.2.3.6 Selection of Scaling Resistor (RSET) and Short-Circuit Protection Setting Resistor (RSCP)
        7. 9.2.3.7 Overcurrent Limit (ILIM), Circuit Breaker Timer (TMR), and Current Monitoring Output (IMON) Selection
        8. 9.2.3.8 Overvoltage Protection and Battery Monitor
      4. 9.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 9.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 9.2.6 TVS Selection
      7. 9.2.7 Application Curves
    3. 9.3 Addressing Automotive Input Reverse Battery Protection Topologies With LM749x0-Q1
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 TVS Selection for 12V Battery Systems
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input Pins A to GND (LM74900-Q1, LM74910-Q1) –65 70 V
A to GND (LM74910H-Q1) –65 74 V
VS, CS+, CS-, ISCP, OUT, SLEEP_OV to GND (LM74900-Q1, LM74910-Q1) –1 70
VS, CS+, CS-, ISCP, OUT, SLEEP_OV to GND (LM74910H-Q1) –1 74
 SW, C, EN, SLEEP, FLT, UVLO, OV to GND, V(A) > 0 V (LM74900-Q1, LM74910-Q1) –0.3 70
 SW, C, EN, SLEEP, FLT, UVLO, OV to GND, V(A) > 0 V (LM74910H-Q1) –0.3 74
SW, C, EN, SLEEP, FLT, UVLO, OV to GND, V(A) ≤ 0 V (LM74900-Q1, LM74910-Q1) V(A) (70 + V(A))

SW, C, EN, SLEEP, FLT, UVLO, OV to GND, V(A) ≤ 0 V (LM74910H-Q1)		 V(A) (74 + V(A))
RTN to GND –65 0.3
ISW ,IFLT  –1 10 mA
TMR, ILIM –0.3 5.5 V
IEN, IUVLO,IOV  V(A) > 0 V –1 mA
IEN, IUVLO,IOV  V(A) ≤ 0 V Internally limited
Input Pins ISCP, CS+ to CS- –0.3 0.3 V
Output Pins OUT to VS –65 5 V
CAP to VS –0.3 15
CAP to A (LM74900-Q1, LM74910-Q1) –0.3 85
CAP to A (LM74910H-Q1) –0.3 88
DGATE to A –0.3 15
FLT to GND (LM74900-Q1, LM74910-Q1) -0.3 70
FLT to GND (LM74910H-Q1) -0.3 74
IMON  -1 5.5
HGATE to OUT –0.3 15
Output to Input Pins C to A (LM74900-Q1, LM74910-Q1) –5 85
C to A (LM74910H-Q1) –5 88
Operating junction temperature, Tj(2) –40 150 °C
Storage temperature, Tstg –40 150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.