SLUSFB7C September   2023  – September 2025 LMG3624

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 GaN Power FET Switching Capability
      2. 7.3.2 Turn-On Slew-Rate Control
      3. 7.3.3 Current-Sense Emulation
      4. 7.3.4 Input Control Pins (EN, IN)
      5. 7.3.5 AUX Supply Pin
        1. 7.3.5.1 AUX Power-On Reset
        2. 7.3.5.2 AUX Under-Voltage Lockout (UVLO)
      6. 7.3.6 Overcurrent Protection
      7. 7.3.7 Overtemperature Protection
      8. 7.3.8 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Turn-On Slew-Rate Design
        2. 8.2.2.2 Current-Sense Design
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • REQ|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 GaN Power FET Switching Capability

Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware that the nameplate drain-source voltage cannot be used as an equivalent point to compare devices across technologies. The nameplate drain-source voltage of a silicon FET is set by the avalanche breakdown voltage. The nameplate drain-source voltage of a GaN FET is set by the long term compliance to data sheet specifications.

Exceeding the nameplate drain-source voltage of a silicon FET can lead to immediate and permanent damage. Meanwhile, the breakdown voltage of a GaN FET is much higher than the nameplate drain-source voltage. For example, the breakdown drain-source voltage of the LMG3624 GaN power FET is more than 800V which allows the LMG3624 to operate at conditions beyond an identically nameplate rated silicon FET.

The LMG3624 GaN power FET switching capability is explained with the assistance of Figure 7-2. The figure shows the drain-source voltage versus time for the LMG3624 GaN power FET for four distinct switch cycles in a switching application. No claim is made about the switching frequency or duty cycle. The first three cycles show normal operation and the last cycle shows operation during a rare input voltage surge. The LMG3624 GaN power FETs can be turned on in continuous-conduction mode (CCM) hard switching, zero-voltage switching (ZVS), and discontinuous-conduction mode (DCM) switching conditions.

LMG3624 GaN Power FET Switching Capability Figure 7-2 GaN Power FET Switching Capability

Each cycle starts before t0 with the FET in the on state. At t0, the GaN FET turns off and parasitic elements cause the drain-source voltage to ring at a high frequency. The high frequency ringing dampens out by t1. Between t1 and t2, the characteristic response of the switching application sets the FET drain-source voltage. The characteristic is shown as a flat line (plateau), but other responses are possible. At t2, the GaN FET turns on. For normal CCM operation, the voltage limit of the transient ring is 650V and the voltage limit of the plateau is 520V. For normal ZVS/DCM operation, the voltage limit of the transient ring is 700V and the voltage limit of the plateau is 560V. For rare surge events, the voltage limit of the transient ring is 800V and the voltage limit of the plateau is 720V.