SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
APLL1 supports a programmable loop bandwidth from 100 Hz to 10 kHz (typical range), and APLL2 supports a programmable loop bandwidth from 100 kHz to 1 MHz (typical range). The loop filter components can be programmed to optimize the APLL bandwidth depending on the reference input frequency and phase noise. The LF1 and LF2 pins each require an external "C2" capacitor to ground. See the suggested values for the LF1 and LF2 capacitors in the Pin Configuration and Functions section.
Figure 44 shows the APLL loop filter structure between the PFD/charge pump output and VCO control input.