SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Each of the six output channels has an output divider after the output mux. The OUT[0:1] channel has a single output divider that is similar to the OUT[2:3] channel output divider. Each OUT[4:7] channel has an individual output divider. The output divider is used to generate the final clock output frequency from the source selected by the output mux.
Each OUT[0:6] channel has an 8-bit divider (OD) that can support output frequencies from 10 to 800 MHz (or up to the maximum frequency supported by the configured output driver type). It is possible to configure the PLL post-divider and output divider to achieve higher clock frequencies, but the output swing of the driver may fall out of specification.
The OUT7 channel has cascaded 8-bit (OD) and 24-bit (OD2) output dividers to support output frequencies from 1 Hz (1 PPS) to 800 MHz. The total OUT7 divide value is the product of the cascaded divider values (OD × OD2).
Each output divider is powered from the same VDDO_x supply used for the clock output drivers. The output divider can be powered down if not used to save power. For either OUT[0:1] or OUT[2:3] channel, the output divider is automatically powered down when both output drivers are disabled. For any OUT[4:7] channel, the output divider is automatically powered down when its output driver is disabled.